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研究生:謝坤展
研究生(外文):Kun-JanShie
論文名稱:整合除5除頻器之60GHz鎖相迴路設計
論文名稱(外文):Design of a 60 GHz Phase-Locked Loop integrated with a Divided-by-5 Prescaler
指導教授:黃尊禧
指導教授(外文):Tzuen-Hsi Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:91
中文關鍵詞:壓控振盪器注入式鎖定除五除頻器鎖相迴路
外文關鍵詞:Voltage-controlled OscillatorInjection-locked divided-by-five frequency dividerPhase-locked Loop
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本論文主要是在設計一個應用於V-band頻帶的低功耗高效能鎖相迴路;並利用TSMC 90-nm RF CMOS製程技術實現此鎖相迴路。整體鎖相迴路子電路包含了一個操作在58.58~60.01 GHz毫米波的壓控振盪器、一個由本實驗室所提出注入式鎖定除五除頻器;一個採用三級電流模式邏輯(CML)除二電路所組成的除八電路、一個由本實驗室所提出的新式真實單相時脈四項位除三電路、一個利用預充型D型正反器所組成的相位頻率偵測器及一個利用誤差放大器作電流的誤差補償以減低非理想效應的充電幫浦電路。在整體V-band的鎖相迴路中,一個高除數除五除頻器不僅能將壓控器輸出頻率快速降頻,在整體鎖相迴路電路的佈局面積及功耗上面也具有優勢。
論文主要分為四個章節,第一章先就目前發展的V-band通訊系統作一普通的介紹。第二章探討目前所認知的鎖相迴路各個子電路(包括 : 壓控振盪器、注入式鎖定除頻器、相位頻率偵測器、充電幫浦、迴路濾波器)之工作原理及電路特性。第三章探討鎖相迴路的迴路頻寬與迴路雜訊的分析。因為迴路頻寬的大小與整體迴路的鎖定速度、雜訊貢獻度這兩者相關性很高。第四章為本論文所實現的整體V-band鎖相迴路的電路架構說明、電路模擬、量測結果以及跟其它文獻的比較結果。
本鎖相迴路的模擬規格特性如下。操作參考訊號頻率為500MHz;鎖定頻率為60 GHz;鎖定時間大約為0.7 ;Reference Spur約為-46.32dBm;整體鎖相迴路電路消耗功率為41.73mW;整體佈局面積約為0.9*0.9mm2。
在量測方面,壓控振盪器的調頻範圍57.92~59.5GHz,輸出功率約為-21dBm左右,核心功率消耗為10.3mW。注入式鎖定除五除頻器的量測,本身除頻free-running的調頻範圍為11.192~11.525GHz,輸出功率約為-16.33dBm左右,核心功率消耗1.96mW。整體鎖相迴路沒有達到鎖定的效果。

The main part of this thesis is to design a low-power high-performance phase-locked loop (PLL) for V-band applications. The PLL circuit was fabricated in TSMC’s 90-nm RF CMOS technology. The circuit includes a voltage-controlled oscillator (VCO) which operates in V-band of 58.58~60.01 GHz and combines a divided-by-five injection-locked frequency divider (ILFD) which has been well developed in our laboratory. The whole circuit is also with a divided-by-eight circuit consisting of three current-mode logic (CML) divided-by-two circuits, a novel true single phase locked (TSPC) divided-by-three circuit, a phase frequency detector consisting of precharged type D flip-flops, and an error amplifier to reduce the current mismatch and the non-ideal effects of the charge pump circuit. A high division-ratio frequency divider not only can divide a high frequency into a lower range quickly but also has the benefit of smaller chip area and power consumption for a PLL circuit.
The thesis was divided into four chapters. The first chapter introduces the presently popular V-band communication systems in general. The second chapter studies the sub-circuits of a phase-locked loop, like a voltage-controlled oscillator (VCO), injection-locked frequency divider (ILFD), phase frequency detector (PFD), Charge Pump (CP), Loop Filter. The third chapter provides the analysis of loop bandwidth and loop noise of a PLL. Because of the loop bandwidth is strongly related to the locking speed and loop noise. The fourth chapter describes the realized 60 GHz PLL circuit, including the structure, the simulation results, the measurement data, as well as the comparisons with the other previous articles.
Based on the simulation results, the desired specifications of this PLL are listed below. The frequency of input reference signal is 500MHz. The target of locked frequency is 60 GHz and the locking time is about 0.7 . The simulated reference spur is -46.32dBm, while the total power consumption is about 41.73mW. The layout area of the whole chip is about 0.9×0.9mm2.
Based on the measurement results, the voltage-controlled oscillator frequency tuning range is 57.92~59.5GHz and output power is -21dBm and power consumption of core is 10.3mW. The free-running frequency tuning range of injection-locked frequency divider is 11.192~11.525GHz and output power is -16.33dBm and power consumption of core is 1.96mW. The measurement of phase-locked loop was not locked.

摘要 I
Abstract III
誌謝 V
目錄 VI
表目錄 VIII
圖目錄 IX

第一章 緒論 1
1.1研究背景 1
1.2研究動機 3
1.3論文架構 3

第二章 鎖相迴路 5
2.1 鎖相迴路 5
2.2 相位雜訊 6
2.3參考頻率突波 7
2.4壓控振盪器 9
2.5除頻器 18
2.6 注入式鎖定除頻器 21
2.7相位頻率偵測器及充電幫浦 33
2.8迴路濾波器 36

第三章 迴路頻寬與迴路雜訊分析 37
3.1迴路濾波器 37
3.2 迴路雜訊 47

第四章 鎖相迴路電路實現與模擬量測 57
4.1毫米波鎖相迴路 57
4.2 毫米波壓控振盪器 58
4.3 注入鎖定除五除頻器 66
4.4電流模式邏輯除二電路及新式真實單相時脈除三電路 73
4.5相位頻率偵測器,Clear and Precharge 75
4.7充電幫浦 78
4.8 模擬與量測結果 81

第五章 結論與未來規劃 85
5.1結論 85
5.2未來規劃 86

參考文獻 87


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