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研究生:萬少華
研究生(外文):Shao-HuaWan
論文名稱:一個減輕參考電壓緩衝器驅動能力要求的十位元一億二千五百萬取樣頻率逐漸趨近式類比至數位轉換器
論文名稱(外文):A 10-bit 125-MS/s SAR ADC with Techniques for Relaxing the Requirement on Driving Capability of Reference Voltage Buffers
指導教授:張順志
指導教授(外文):Soon-Jyh Chang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:111
中文關鍵詞:逐漸趨近式類比至數位轉換器參考電壓緩衝器功率消耗
外文關鍵詞:successive approximation registerSARanalog-to-digital converterA/DADCreference voltage bufferreference bufferpower consumptionpower dissipation
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本篇論文提出數個減緩逐漸趨近式類比至數位轉換器之參考電壓緩衝器驅動能力需求的設計技術,並且基於提出的技術,實現一個十位元一億兩千五百萬取樣頻率的非同步逐漸趨近式類比至數位轉換器。一般二進位搜尋演算法需要經過數個週期循環轉換出數位碼,其中在決定最高權重位元時,需要一個具有高驅動能力的參考電壓緩衝器,以在有限的充電時間內,將最大電容的電壓穩定至電路需求的精確度。因此,參考電壓緩衝器的功率消耗經常是數倍於類比至數位轉換器本身所消耗的量。為了解決這問題,本論文提出「四分之一趨近」結合「二進位搜尋」演算法,減少在一個穩定時間內的電容負載和要求的穩定精確度,進而降低對參考電壓緩衝器驅動能力的需求。再者,在數位邏輯的部分,採用「直接電容切換」的技巧,能在電路內部每次循環中增加電容陣列之電壓穩定時間的比例。此外,本篇提出由新穎之三維單位電容組成的網狀電容陣列,在很小的容值下能保有相當高的線性度,並且可以大幅減少佔據晶片的面積。至於電容的切換機制是基於「分離單調式」結合「單調式」電容切換,以減少共模電壓的偏移。
所設計的晶片下線於台積電40nm-LP 1P7M CMOS製程,且主要核心部分佔據的面積只有127µm × 90µm。模擬結果顯示,採用本論文提出的三種技術,在一次轉換中對於參考電壓緩衝器所需求的平均電流與最大電流分別減少96.3%與94.2%。在量測結果中,如果操作頻率在每秒五千萬次時,DNL和INL分別為+0.49/-0.81 LSB與 +0.93/-0.86 LSB,等效位元數為9.18-bit;若操作頻率在每秒一億兩千五百萬次時,DNL和INL分別為+2.05/-1 LSB與+2.04/-1.6 LSB,等效位元數為8.42-bit。而在這兩種不同的取樣頻率中,每次轉換所需的能量分別為16fJ和38fJ。
This thesis presents some techniques which mitigate the requirement on driving capability of reference voltage buffers for SAR ADCs. Also, we realize a 10-bit 125MS/s asynchronous SAR ADC based on the proposed techniques. A conventional SAR ADC with binary search algorithm needs several cycles to generate the digital code. When the SAR ADC determines the MSB, it requires a reference voltage buffer with high driving capability to charge the largest capacitor within the required accuracy in the given settling time. As a result, the power consumption of reference voltage buffer is usually several times larger than the core SAR ADC. In order to resolve this problem, this work proposes a new algorithm which is a “quarter approximation” combined with “binary search algorithm”. This technique can decrease the requirement on driving capability of reference voltage buffer by reducing the maximum capacitive load and the required settling accuracy in the given settling time. Moreover, we apply the “direct capacitor switching” technique in SAR digital logic to increase the ratio of settling time in the internal period. Besides, we propose a “meshed capacitor array” composed of “new 3D capacitors” to greatly reduce the occupied area and capacitance, but a good linearity is still maintained. The capacitor switching procedure is based on the “splitting-monotonic” combined with the “monotonic” one to reduce the common mode variation.
The proposed chip is fabricated in TSMC 40nm-LP 1P7M CMOS fabrication process, and the core area is 127µm × 90µm. With using the proposed three techniques in this work, the simulation results of reference voltage buffers indicates that the average current and peak current of reference voltage buffer decrease 96.3% and 94.2% respectively. In the measurement results, if the sampling rate is 50MS/s, the measured DNL, INL, and ENOB are +0.49/-0.81 LSB, +0.93/-0.86 LSB, and 9.18-bit. If the sampling rate is 125MS/s, the measured DNL, INL, and ENOB are +2.05/-1 LSB, +2.04/-1.6 LSB, and 8.42-bit. Furthermore, in these different sampling rates, the measured FoM(s) are 16fJ/Conv.-Step and 38fJ/Conv.-Step respectively.
Contents

List of Figures X

List of Tables XIV

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 7

Chapter 2 Fundamental and Specification of Analog-to-Digital Converter 8
2.1 Introduction 8
2.2 The Concept of Analog-to-Digital Converter 9
2.3 Resolution and Accuracy 10
2.3.1 Resolution 10
2.3.2 Accuracy 12
2.4 Static Specification 12
2.4.1 Offset 12
2.4.2 Gain Error 13
2.4.3 Nonlinearity 14
(1) Differential Nonlinearity (DNL) 15
(2) Integral Nonlinearity (INL) 16
2.5 Dynamic Specification 18
2.5.1 Signal-to-Noise Ratio (SNR) 18
2.5.2 Signal-to-Noise Ratio and Distortion Ratio (SNDR) 20
2.5.3 Spurious-Free Dynamic Range (SFDR) 20
2.5.4 Total Harmonic Distortion (THD) 21
2.5.5 Effective Number of Bits (ENOB) 21
2.5.6 Figure-of-Merit (FoM) 22

Chapter 3 Nyquist Rate Analog-to-Digital Converter 23
3.1 Introduction 23
3.2 Flash ADC 24
3.3 Subranging ADC 25
3.4 Pipelined ADC 26
3.5 Successive Approximation Register (SAR) ADC 29
3.5.1 SAR Algorithm With Capacitive DAC 30
3.5.2 The Fundamental Technologies of SAR ADC 32
(1) Charge Redistribution 32
(2) Synchronous VS. Asynchronous 33
(3) Single-Ended Signal VS. Differential Signal 35
(4) Bottom-Plate Sampling VS. Top-Plate Sampling 35
3.5.3 The Switching Procedure of SAR ADC 37
(1) Conventional Capacitor Switching Procedure 37
(2) Monotonic Capacitor Switching Procedure 39
(3) VCM-Based Capacitor Switching Procedure 41
(4) Splitting-Monotonic Capacitor Switching Procedure 42
3.5.4 The Analysis of Switching Energy 44

Chapter 4 Construction of Proposed 10-bit 125MS/s SAR ADC 46
4.1 Motivation 46
4.2 Proposed Switching Algorithm 48
4.2.1 Switching Procedure 49
4.2.2 Switching Energy Consumption 53
4.2.3 Switching Settling Time 57
4.3 Proposed New 3D Capacitor and Meshed Capacitor Array 62
4.4 Circuit Implementation 67
4.4.1 Introduction 67
4.4.2 Sample and Hold (S/H) Circuit 68
4.4.3 Capacitor Array 72
4.4.4 Comparator 74
4.4.5 Digital Logic Control Circuit 76
(1) Direct Capacitor Switching Method 76
(2) SAR Logic Control 80
(3) Direct Capacitor Switching Control 81
4.5 Driving Capability of Reference Voltage Buffers 81
4.6 Layout Graph and Floor Plan 86
4.7 Post-Layout Simulation Results 88
4.8 Measurement Results 91
4.8.1 Micrograph of Chip and Measurement Setup 91
4.8.2 Measurement Performance 93

Chapter 5 Conclusion and Future Work 102

Bibliography 106
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