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研究生:蔡俊猷
研究生(外文):Chun-YuTsai
論文名稱:應用於WLAN 802.11a系統之分數型頻率合成器設計
論文名稱(外文):Fractional-N Frequency Synthesizer Design for WLAN 802.11a Systems
指導教授:黃尊禧
指導教授(外文):Tzuen-Hsi Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:94
中文關鍵詞:分數型頻率合成器
外文關鍵詞:Fractional-N synthesizers
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傳統的整數型頻率合成器會遇到幾個基本的特性取捨問題。例如,頻率解析度與其他特性如迴路頻寬、相位雜訊、參考信號突波以及鎖定時間等皆有設計上折衷的考量。由於整數型合成器的輸出頻率一定是輸入頻率的整數倍,因此頻率合成器的特性會受到上述條件的限制。為了打破這些限制,不同的分數型頻率合成器架構也因此被提出來。在這些分數型的架構當中,三角積分分數型頻率合成器為本論文使用的架構,因為它的分數突波較小,且三角積分調變器具有將量化雜訊移往高頻去的特性,但是分數突波和量化雜訊仍然是分數型頻率合成器設計當中兩個最主要的問題。
本論文設計研究應用於802.11a WLAN之Fractional-N頻率合成器,並以TSMC 0.18um 1P6M CMOS製成,包含相頻偵測器(PFD)、電荷幫浦(CP)、低通迴路濾波器(LPF)、壓控振盪器(VCO)、及三角積分多模數除頻器。頻率合成器提供5.265GHz至5.325GHz的本地振盪訊號,適用在802.11a WLAN接收機上,其頻率解析度為250 kHz。壓控振盪器之設計上利用電晶體開關切換,使LC tank的電容值在開關切換前後有一定的程度變化,以克服製成偏移所造成頻率偏差的影響;電荷幫浦方面使動態電流匹配電荷幫浦,其設計簡單且具有低功耗之優點;在三角積分調變器的方面,為了避免電路的不穩定發生,使用多級雜訊整形(MASH)架構。
量測壓控振盪器其在1 MHz頻率偏移處的相位雜訊為-116.14 dBc/Hz,可調頻率範圍為4.95GHz至5.638GHz,輸出功率為-5.06 mW。頻率合成器消耗為24.5 mW (包含輸出緩衝級),電壓使用1.8V。佈局的面積約為0.88 mm × 0.87 mm (包含bonding pads) 。
The conventional integer-N frequency synthesizers need the design tradeoffs among their fundamental performances like the frequency step size, loop bandwidth, phase noise, reference spurs and locking time. Since the output frequency is an integer multiple of the input frequency, the performances of the integer-N frequency synthesizers are limited. To solve the above problem, the different types of fractional-N frequency synthesizer structures have been therefore proposed. Among these different structures, the delta-sigma fractional-N frequency synthesizers possess smaller magnitude of fractional spurs and better high-pass noise shaping ability. So we try to design the frequency synthesizer with the the delta-sigma fractional-N structure. However, the quantization phase noise and fractional spurs are still the main problems in this sort of frequency synthesizer design.
This thesis presents the study on CMOS fractional-N synthesizer for 802.11a WLAN applications and the related chip implementation with the frequency resolution of 250 kHz in TSMC standard 0.18um CMOS technology. This frequency synthesizer includes a phase frequency detector, a charge pump, a low pass loop filter, a voltage control oscillator and a delta-sigma multi-modulus frequency divider. The proposed frequency synthesizer is used for IEEE 802.11a wireless LAN application with the frequency ranging from 5.265GHz to 5.325GHz. A switching capacitor array is used in the design of VCO for tuning the total capacitance of the LC tank to compensate the frequency deviation due to process variation. In the design of charge pump, the dynamic current-matching charge pump is adopted because it has the advantage of low power consumption and easy design. In the design of sigma-delta modulator, in order to avoid the circuit unstable, the Multi-stAge Noise Shaping (MASH) architecture is adopted.
The measured VCO tuning range is from 4.95GHz to 5.638GHz, the output power is -5.06 dBm and phase noise is -116.14 dBc/Hz at 1 MHz offset frequencies. The total power consumption of frequency synthesizer is 24.5 mW (including that of output buffers) with a 1.8V power supply. The layout area is of 0.88 mm × 0.87 mm, including the pads.
摘要 I
Abstract III
致謝 V
表目錄 VIII
圖目錄 IX

第一章 緒論 1
1.1 研究背景與動機 1
1.1.1 WLAN 802.11介紹 1
1.2 論文架構 3

第二章 頻率合成器簡介 5
2.1 整數型頻率合成器 6
2.2 分數型頻率合成器 7
2.3 三角積分(Delta-Sigma, )之分數型頻率合成器 9

第三章 三角積分調變器與頻率合成器雜訊分析 12
3.1 三角積分調變器 12
3.1.1 數位相位累加器 13
3.1.2 一階三角積分調變器 14
3.1.3 二階三角積分調變器 18
3.1.4 三階三角積分調變器 21
3.2鎖相迴路線性方程式與系統穩定度分析 26
3.2.1 相位偵測器、電荷幫浦與迴路濾波器 27
3.2.2 壓控振盪器 29
3.2.3 頻率除頻器 30
3.2.4系統穩定度分析 31
3.3 頻率合成器雜訊分析 40
3.3.1 各個子電路雜訊對系統之貢獻 40

第四章 分數型頻率合成器設計 49
4.1 架構簡介 49
4.1.1應用於WLAN 802.11a系統之分數型頻率合成器設計 49
4.1.2 相位頻率偵測器電路設計 50
4.1.3 電荷幫浦電路設計 52
4.1.4 迴路低通濾波器設計 58
4.1.5壓控振盪器設計 63
4.1.6 前置除頻器電路設計設計 67
4.1.7差異積分多除數除頻器電路設計 70
4.2系統電路行為模擬結果 82
4.3分數型頻率合成器模擬結果 84

第五章 量測結果 86
5.1 量測摘要與考量 86
5.2 互補式壓控振盪器量測 87

第六章 結論與未來展望 91
6.1 結論 91
6.2 未來規劃 91

參考文獻 92


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