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研究生:林文景
研究生(外文):Wen-ChingLin
論文名稱:高效能公開金鑰密碼系統處理器之積體電路架構設計
論文名稱(外文):High-performance VLSI Architecture Design of Public-Key Cryptography Processor
指導教授:謝明得謝明得引用關係
指導教授(外文):Ming-Der Shieh
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:136
中文關鍵詞:除法有限場模數乘法公開金鑰密碼超大型積體電路
外文關鍵詞:divisionfinite fieldmodular multiplicationpublic-key cryptographyVLSI
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公開金鑰密碼(public-key cryptography, PKC)能提供安全功能像是機密性、認證、資料完整性和不可否認性,因此它在無線通訊系統和網路服務中扮演越來越重要的角色。本論文提出高效能的GF(2m)除法、模數乘法和公開金鑰密碼處理器之超大型積體電路設計。我們提出減輕傳統迭代GF(2m)除法和基於字元(word-based)之蒙哥馬利(Montgomery)模數乘法演算法的資料相依(data dependency)的技術,以達到高效率硬體實現。我們藉由改變預先定義的變數,然後相對應地更新其初始值,來改寫傳統迭代(iterative)的GF(2m)除法演算法。在改寫的演算法裡,用來更新新定義變數的兩個運算,判斷加法是否要執行和減少多項式次數,可以同時執行;因此開發出的除法器在不增加延遲(latency)和面積的成本之下,進一步提高運行速度。
在減輕傳統基於字元之蒙哥馬利模數乘法演算法的資料相依的情況下,使相鄰的處理單元(process element, PE)的延遲時間為剛好一個週期;且在字元須大於一個位元的前提下,無論選擇字元的大小。加上使用所提出的縮減運算元數目方案,我們的可擴充性架構可以運作在非常高的速度;而且不同的應用可以使用各自適合的資料路徑(datapath)。除此之外,這項研究也提出最大程度的減輕傳統基於字元之蒙哥馬利演算法的資料相依,以達到最大限度重複使用變數現在的這個字元。在最大程度的減輕資料相依之下,我們提出一個新的排程方案來減少所開發的可擴充性架構的記憶體存取次數。假設w代表一個字元的大小,分析結果顯示,所提出的可擴充性架構的記憶體存取次數約為傳統的可擴充性架構的(w-1)分之一倍。
最後,本論文提出一個配備可重組化處理單元陣列(reconfigurable process element array, RPEA)的公開金鑰密碼處理器;可重組化處理單元陣列可根據運算元大小,重組成一個、兩個或四個基於所提出的基於字元展開(unrolling)平行化蒙哥馬利演算法的低延遲模數乘法器;使用盡可能多的模數乘法器之排程來執行模指數和橢圓曲線向量乘法的運算。因此,可重組化處理單元陣列可有效率地執行各種精確度的任意質數、不可分解多項式和曲線參數之模指數和雙場(dual-field)橢圓曲線向量乘法。比較的結果顯示所提出的處理器不但能支援多種公開金鑰密碼演算法與廣泛大小的運算元,且與其它文獻內的公開金鑰密碼處理器比較起來是更有效率的。

Public-key cryptography (PKC) has become increasingly important in wireless communication systems and internet services for providing security such as confidentiality, authentication, data integrity, and non-repudiation. This dissertation presents high-performance VLSI designs of GF(2m) division, modular multiplication, and a PKC processor. Techniques for relaxing the data dependency in conventional iterative GF(2m) division and word-based Montgomery modular algorithms are presented to achieve highly efficient hardware implementations. The conventional GF(2m) division algorithm is reformulated by changing the pre-defined variable and then updating its initial value accordingly. In the reformulated division algorithm, determining whether the addition is needed to be performed and the reduction for updating the new-defined variable can be carried out concurrently; thus the developed dividers improve its operating speed without increasing latency or area cost.
With the data dependency relaxed in conventional word-based Montgomery modular multiplication algorithms, a latency of exactly one cycle between neighboring processing elements can be obtained regardless of the chosen word size w (w 〉 1). With the proposed operand reduction scheme, scalable architectures can operate at high speeds and proper datapaths can be chosen for specific applications. Besides, the data dependency in conventional word-based Montgomery’s algorithms is greatly relaxed to maximize the possibility of reusing the current words of variables. With the greatly relaxed data dependency, a scheduling scheme is proposed to further reduce the number of memory accesses in the developed scalable architecture. Analytical results show that the memory bandwidth requirement of the proposed scalable architecture is almost 1/(w-1) times that of conventional scalable architectures.
Finally, a reconfigurable process element array (RPEA) is developed in the proposed PKC processor. Given an operand size, the RPEA can be configured as one, two, or four low-latency modular multipliers based on the proposed word-based unrolling parallelized Montgomery algorithm. An associated scheduler can then use as many modular multipliers as possible to carry out modular exponentiation and elliptic curve scalar multiplication. Consequently, the RPEA can efficiently perform modular exponentiation and dual-field elliptic curve scalar multiplication for arbitrary prime numbers, irreducible polynomials, and curve parameters with multiple precisions. Comparison results show that the proposed PKC processor is more efficient than existing PKC processors and can support various public-key algorithms with a wide range of operand sizes.
1. INTRODUCTION 1
1.1 MOTIVATION 1
1.2 PREVIOUS WORKS 4
1.3 PROPOSED DESIGNS OF MODULAR ARITHMETIC AND PUBLIC-KEY CRYPTOGRAPHY PROCESSOR ARCHITECTURES 5
1.3.1 GF(2m) Dividers 5
1.3.2 Montgomery Modular Multipliers 6
1.3.3 PKC Processor 10
1.4 ORGANIZATION OF THE DISSERTATION 11
2. PRELIMINARY OF MODULAR ARITHMETIC AND PUBLIC-KEY CRYPTOGRAPHY 12
2.1 MODULAR ARITHMETIC 12
2.1.1 Montgomery Modular Multiplication 13
2.1.2 Word-based Montgomery Modular Multiplication 15
2.1.3 Modular Inversion/Division 18
2.2 PUBLIC-KEY CRYPTOGRAPHY 20
2.2.1 RSA 21
2.2.2 ECC 23
3. DESIGN OF HIGH-SPEED ITERATIVE DIVIDERS IN BINARY EXTENSION FIELDS 28
3.1 PROPOSED DIVISION ALGORITHM 28
3.2 DEVELOPED ITERATIVE DIVIDERS 33
3.2.1 Base Cell Design 33
3.2.2 Semi-Systolic Array Design 36
3.2.3 Bit-Serial Systolic Array Design 36
3.3 PERFORMANCE ANALYSIS AND IMPLEMENTATION RESULTS 40
3.4 FLEXIBLE GF(2M) DIVIDER DESIGN FOR CRYPTOGRAPHIC APPLICATIONS 46
3.4.1 Proposed SIMD/SISD Divider Architecture 47
3.4.2 Complexity Analysis and Implementation Results 52
3.5 SUMMARY 54
4. WORD-BASED MONTGOMERY MODULAR MULTIPLICATION ALGORITHM FOR LOW-LATENCY SCALABLE ARCHITECTURES 55
4.1 PROPOSED WORD-BASED MONTGOMERY MODULAR MULTIPLICATION ALGORITHM 56
4.1.1 Dependency Relaxation 56
4.1.2 Operand Reduction 57
4.1.3 New Word-Based Montgomery Modular Multiplication Algorithm 60
4.1.4 Scheduling and Performance Estimation 61
4.2 COMPLEXITY ANALYSIS AND EXPERIMENTAL RESULTS 65
4.2.1 Hardware Design 65
4.2.2 Complexity Analysis and Comparison 67
4.2.3 Experimental Results 71
4.3 FAST SCALABLE RADIX-4 MONTGOMERY MODULAR MULTIPLIER 74
4.3.1 Proposed Word-based Radix-4 Montgomery Modular Multiplication Algorithm 75
4.3.2 Scheduling, Hardware Architecture and Implementation Results 78
4.4 SUMMARY 84
5. SCALABLE MONTGOMERY MODULAR MULTIPLICATION ARCHITECTURE WITH LOW LATENCY AND LOW MEMORY BANDWIDTH REQUIREMENT 85
5.1 PROPOSED WORD-BASED MONTGOMERY MODULAR MULTIPLICATION ALGORITHM 86
5.1.1 Data Dependency Relaxation for Low Memory Bandwidth Requirement 86
5.1.2 Proposed Word-Based Montgomery Modular Multiplication Algorithm 89
5.1.3 Scheduling and Performance Estimation 91
5.2 HARDWARE ARCHITECTURE AND EXPERIMENTAL RESULTS 95
5.2.1 Hardware Design 95
5.2.2 Experimental Results and Comparisons 97
5.3 SUMMARY 102
6. HIGH-PERFORMANCE PUBLIC-KEY CRYPTOGRAPHY PROCESSOR WITH RECONFIGURABLE PROCESS ELEMENT ARRAY 103
6.1 PROPOSED WORD-BASED ALGORITHM FOR MONTGOMERY MODULAR MULTIPLICATION 104
6.1.1 Proposed Word-based Radix-2 Parallelized Montgomery Modular Multiplication Algorithm 104
6.1.2 Latency of Montgomery Modular Multiplication 108
6.2 PKC PROCESSOR ARCHITECTURE 110
6.2.1 Functional Units 111
6.2.2 Scheduling and Latency for Cryptographic Functions 115
6.2.3 Local Memory 119
6.3 IMPLEMENTATION RESULT AND COMPARISON 120
6.4 SUMMARY 125
7. CONCLUSION AND FUTURE WORK 126
7.1 CONCLUSION 126
7.2 FUTURE WORK 129
BIBLIOGRAPHY 131
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