臺灣博碩士論文加值系統

隨著多媒體技術的發展，輕薄短小已成為行動裝置的基本訴求，如何將高複雜度的運算以硬體加速化來支援多種規格與功能的多媒體產品，儼然成為一個重要的議題。本論文針對多規格與成本資源上的考量，提出修正型離散正弦正/逆轉換、修正型離散餘弦正/逆轉換和遞迴式傅立葉轉換的共架構設計。運用簡單的前後處理，將五種轉換推導為共架構的形式；並透過演算法本身的對稱性與係數週期性，利用遞迴運算自動產生係數值，用以大量減少多規格所衍生的係數記憶體龐大問題，進而探討硬體的共用性並減少其運算複雜度，達到硬體資源共享。在硬體實現上，可支援MPEG-1 Layer I-III、AAC和E-AC-3的濾波器組與心理聲響模型分析所需的頻譜轉換，整體電路架構僅需2個乘法器和4個加法器，以製程為TSMC 0.18μm 1P6M CMOS的技術下邏輯閘數目約30.3K，操作頻率為52.63MHz，適合應用於支援多格式的音訊行動裝置。

Digital audio coding has become more and more popular and indispensable feature of consumer electronics in recent years. For the portable devices and consumer interest, a multi-standard design on a single device has found widespread use in popular audio applications. In this thesis, we propose a compact common-architecture design for computing the modified discrete cosine transform (MDCT), modified discrete sine transform (MDST), inverse modified discrete cosine transform (IMDCT), inverse modified discrete sine transform (IMDST) and discrete fourier transform (DFT). With a simple preprocessor, the proposed algorithm, which can be derived into a common computation, requires low computational complexity and is applied on MPEG-1 Layer I to III ( 12 / 36 – MDCT / MDST / IMDCT / IMDST, 512 / 1024 – DFT ), AAC ( 256 / 2048 – MDCT / MDST / IMDCT / IMDST, 256 / 2048 - DFT) and E-AC-3 ( 256 / 512 – MDCT / MDST / IMDCT / IMDST ). In the architecture, a high-throughput, coefficient memory-free and hardware-sharing architecture is developed include which can be configured for different transforms. Furthermore, this design is synthesized using TSMC 0.18μm 1P6M CMOS technology and takes about 30.3K gates while the max clock rate is 52.63MHz.

中文摘要 I
ABSTRACT III
誌謝 V
目錄 VII
表目錄 XI
圖目錄 XIII
第一章 緒論 1
1.1 研究背景與動機 1
1.1.1 聲音原理 1
1.1.2 音訊處理 2
1.1.3 聽覺系統與遮蔽效應 4
1.1.4 音訊壓縮格式 6
1.1.5 濾波器組 13
1.1.6 研究目的 14
1.2 論文章節組織 16
第二章 文獻演算法分析與介紹 17
2.1 Nikolajevic et al. MDCT / MDST / IMDCT / IMDST 演算法 [25] 17
2.1.1 MDCT演算法推導 18
2.1.2 MDST演算法推導 22
2.1.3 IMDCT演算法推導 26
2.1.4 IMDST演算法推導 29
2.1.5 探討文獻 31
2.2 Koening et al. MDCT / MDST / IMDCT / IMDST 演算法 [28] 34
2.2.1 MDCT演算法推導 34
2.2.2 MDST演算法推導 36
2.2.3 IMDCT演算法推導 37
2.2.4 IMDST演算法推導 38
2.2.5 探討文獻 38
2.3 曾提出並刊登之研究成果 40
2.3.1 以DCT為核心之MDCT / MDST / IMDCT / IMDST共架構演算法[29] 40
2.3.2 以DST為核心之MDCT / MDST / IMDCT / IMDST共架構演算法[30]及其延伸 51
第三章 提出改良型可適用於MDCT / MDST / IMDCT / IMDST / DFT五種轉換的共架構演算法推導 63
3.1 MDCT / MDST / IMDCT / IMDST轉DST-IV演算法推導 63
3.1.1 MDCT轉DST-IV的前處理 64
3.1.2 MDST轉DST-IV的前處理 67
3.1.3 IMDCT轉DST-IV的後處理 71
3.1.4 IMDST轉DST-IV的後處理 72
3.1.5 DST-IV的共架構形式 74
3.2 基於DST轉換的MDCT / MDST / IMDCT / IMDST共用性 75
3.2.1 DST-IV轉IDST-II變形的推導過程 76
3.2.2 DST-IV轉IDST-II變形的［補註］ 77
3.2.3 IDST-II變形（Signed_IDST[k]）推導 77
3.3 MDCT / MDST / IMDCT / IMDST / DFT：核心共架構推導 79
3.3.1 MDCT / MDST / IMDCT / IMDST核心遞迴部分W[k] 80
3.3.2 DFT核心遞迴演算法推導 89
3.3.3 統整MDCT / MDST / IMDCT / IMDST / DFT核心遞迴架構 92
3.4 免係數記憶體遞迴運算（Coefficient Memory- Free） 93
3.4.1 MDCT / MDST / IMDCT / IMDST / DFT各轉換所使用的係數 94
3.4.2 遞迴係數演算法推導 95
3.4.3 演算法特色 97
第四章 共架構硬體設計與規劃 99
4.1 硬體流程規劃 99
4.1.1 MDCT / MDST / IMDCT / IMDST轉DST-IV 99
4.1.2 DST-IV轉為遞迴架構前處理 100
4.1.3 遞迴架構（MDCT / MDST / IMDCT / IMDST / DFT） 102
4.1.4 MDCT / MDST / IMDCT / IMDST後處理 105
4.2 整體規劃與設計 109
4.2.1 仿硬體模擬小數位數的選取 109
4.2.2 免係數記憶體遞迴運算 111
4.2.3 SRAM的大小選取 113
4.2.4 動態調整前處理後的小數位數 114
4.2.5 整體流程圖 116
第五章 分析比較與結果 117
5.1 運算複雜度分析 117
5.1.1 各演算法運算量分析與比較 117
5.1.2 舉例-512點乘法運算量比較 120
5.2 運算週期和硬體需求分析與比較 121
5.2.1 運算週期分析與資料吞吐量 121
5.2.2 硬體需求分析與比較 123
5.2.3 硬體實現與精確度分析 124
第六章 結論與未來展望 127
參考文獻 129

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