跳到主要內容

臺灣博碩士論文加值系統

(35.175.191.36) 您好!臺灣時間:2021/07/30 19:41
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:蘇暐翔
研究生(外文):Wei-ShiangSu
論文名稱:應用於非侵入式眼壓量測系統的感測器振盪電路、鎖相迴路、頻率電壓轉換器電路設計
論文名稱(外文):Designs of Sensor Oscillator, PLL, and Frequency-to-Voltage Converter for Non-invasive IOP Measurement Systems
指導教授:黃尊禧
指導教授(外文):Tzuen-Hsi Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:130
中文關鍵詞:眼壓量測系統壓控振盪器鎖相迴路頻率電壓轉換器
外文關鍵詞:IOP Measurement SystemVoltage-controlled OscillatorPhase-locked LoopFrequency-to-Voltage Converter
相關次數:
  • 被引用被引用:0
  • 點閱點閱:281
  • 評分評分:
  • 下載下載:41
  • 收藏至我的研究室書目清單書目收藏:0
本論文主要是實現應用於非侵入式無線眼壓監控系統(Intraocular Pressure System, IOP System)之部分功能電路的積體化。在本研究團隊的應用系統規畫下,此IOP系統大致上分為三部分:感測端電路(Sensor)、讀取端電路(Reader)、後端資料處理單元(Calculation-Unit)。其中感測端電路包含整流器(Rectifier)、線性穩壓器(Low Dropout Linear Regulator, LDO)、壓控振盪器(Voltage-Controlled Oscillator, VCO);讀取端電路包含接收電路與發射電路,接收電路有低雜訊放大器(Low Noise Amplifier, LNA)、混波器(Mixer)、2.2GHz鎖相迴路(2.2GHz Phase Locked Loop)、頻率對電壓轉換器(Frequency-to-Voltage converter),發射電路有5.8GHz鎖相迴路(5.8GHz Phase Locked Loop)及一個為了推動外接功率放大器的緩衝放大器(pre-amplifier)。
本論文負責感測端的2.4GHz壓控振盪器、讀取端發射電路的5.8GHz鎖相迴路、讀取端接收電路的2.2GHz鎖相迴路及頻率對電壓轉換器的研究與製作,並將讀取端接收及發射電路、感測端電路分別作整合晶片下線,目標為完成感測眼壓值並轉為電壓值的積體電路設計。
所有晶片皆使用國家晶片中心(CIC)所提供的標準製程TSMC 0.18-µm 1P6M CMOS進行製作。5.8GHz鎖相迴路及2.2GHz鎖相迴路電路設計方面:相位頻率偵測器部分,加入clear訊號,以減少初始資料的不確定性對鎖相迴路效能的影響。利用更長的延遲單元解決禁止區(dead zone)的問題。電荷幫浦部分,皆使用誤差放大器改良電荷幫浦電流不匹配之問題,以減少訊號的抖動及得到較好的相位雜訊表現。迴路濾波器部分,分別使用off-chip迴路濾波器及利用電容放大技巧的on-chip迴路濾波器兩種設計情況下線,並於晶片量測後作比較。壓控振盪器分別使用PMOS-only LC VCO及CMOS complementary LC VCO兩種結構。輸入參考訊號分別為100MHz與50MHz,以利讀取端的接收電路及發射電路整合於一顆晶片上。除頻器則依據輸入參考訊號與輸出頻率來決定使用電流模式邏輯閘(Current Mode Logic, CML)及多係數除頻器(Multi-modulus frequency divider)此兩種除頻器。整體電路操作電壓在1.8V,除了電流模式邏輯閘及緩衝器操作在1.5V,以降低整體使用功率。在兩次下線中,整合晶片面積各為1.82 mm2 (1.455mm × 1.25mm)及3.1 mm2 (2.05mm × 1.51mm) 。在鎖定時,壓控振盪器的輸出功率各為-5.731dBm及-11.89dBm;總消耗功率為39.58mW及36.85mW。針對2.2GHz PLL之設計,量得相位雜訊在1MHz位移頻率下為-105dBc/Hz;由輸入參考訊號所產生至鎖相迴路輸出之突波(spur)為-43dBm。
頻率對電壓轉換器電路設計方面,利用混波器將訊號降至中頻,使其為參考頻率。相位頻率偵測器與電荷幫浦使用與鎖相迴路相同之結構。壓控振盪器部分利用汲取電流式延遲單元(Current-starved delay cell)所構成之環形壓控振盪器。在此應用中,主要是讀取迴路濾波器之電壓值變化,因此並沒有選擇以相位雜訊表現較佳的差動延遲單元(differential delay cell)所構成之環形壓控振盪器。迴路濾波器部分,控制電壓點使用單倍增益緩衝器來排除負載效應的影響。整合上述的各功能電路完成頻率對電壓的變化。整體電路操作電壓在1.8V,整體晶片面積為2.91mm2 (1.48mm × 1.97mm)。
感測端電路設計方面,壓控振盪器採用CMOS complementary LC VCO結構。電源供應為無線傳能的方式,為符合SAR值標準,電路規格相對設定在操作電壓為1.5V及操作電流為1.2mA之低功耗設計; 利用L型匹配網路(Matching network)與天線整合模擬。整體晶片面積為1.53mm2(1.29mm × 1.183mm)。

The main purpose of this thesis is to design a part of integrated circuits for a non-invasive wireless intraocular pressure (IOP) monitoring system. In our plan, the IOP system has three main parts: the sensor unit, the reader unit, and the calculation unit. The sensor unit includes a rectifier, a low dropout linear regulator (LDO) and a voltage-controlled oscillator (VCO). The reader unit comprises a receiver and a transmitter. The receiver is composed of a low noise amplifier (LNA), a mixer, a 2.2GHz phase-locked loop (PLL), and a frequency-to-voltage converter. The transmitter consists of a 5.8GHz PLL and an pre-amplifier for driving an off-chip PA.
This thesis targets on the designs of a 2.4GHz voltage-controlled oscillator (VCO) at the sensor unit and a 5.8GHz PLL at the transmitter unit, a 2.2GHz PLL and frequency-to-voltage converter at the receiver unit. The last two circuits are for the reader unit. The circuits mentioned above are all fully-integrated in a CMOS process, respectively. The goal of our integration is to convert the intraocular pressure into a voltages value that can be processed by the calculation unit.
In this thesis, all of the chips are fabricated in TSMC 0.18-μm 1P6M CMOS technology. In the 5.8GHz PLL and the 2.2GHz PLL circuits design, we add a “clear” signal to avoid the PLL performance influencing from the uncertainty of trigger signals. We also use a longer delay-cell chain to solve the “dead zone” problem in the phase-frequency detector (PFD) design. The charge pump circuit design is implemented by a rail-to-rail error amplifier to overcome the process variation and the current mismatch problem, so that the jitter and phase noise performance of VCO are improved simultaneously. For the loop filter design, we use an off-chip loop filter and an on-chip loop filter, respectively, with the capacitive multiplication technique in our two different PLL designs. The voltage-controlled oscillator designs are implemented by PMOS-only LC VCO and CMOS complementary LC VCO, respectively, too. In these two different designs, one of the reference signals is 100MHz and the other is 50MHz, in order to achieve the integration of 2.4GHz receiver and 5.8GHz transmitter circuits into a single chip for the reader unit. For the divider designs, the use of CML or MMFD topology is determined by which reference frequency we used. All PLLs mentioned above are working under a 1.8V power supply, expect for the CMLs and buffers with power-supply lies of 1.5V for reducing power consumption. The chips occupy an area of 1.82 mm2 (1.455mm × 1.25mm) and 3.1 mm2 (2.05mm × 1.51mm), respecitvely, in our two designs. The output power levels of VCOs are -5.731dBm and -11.89dBm, respectively, for the two different designs. The total power consumptions are 39.58mW and 36.85mW. The measured phase noise is -105dBc/Hz at 1MHz offset with a reference spur of -43dbm for the 2.2GHz PLL.
In the frequency-to-voltage converter design, the RF signal down-converted by the mixer to the IF signal will be used as input reference frequency. The phase frequency detector and the charge pump are implemented by the ways similar to those PLLs mentioned above. While, the VCO is a current-starved ring oscillator. In our application, this converter mainly read out the variation of control voltage of the VCO, so the ring oscillator is not based on the differential delay cell topology which has better phase noise performance. In the loop filter design, a unit-gain buffer is used to readout the voltage variation at the output of loop filter with less loading effect. The circuit operates at a 1.8V power-supply and it consumes an area of 2.91mm2 (1.48mm × 1.97mm).
In the sensor circuit design, the proposed VCO is implemented with a CMOS complementary LC VCO architecture. The wireless power transmission technique is adopted for power supply. To fit for the SAR standard, we set our specification of supply voltage at 1.5V with DC current 1.2mA to achieve the low-power design. And we also use a L-type matching network to do the co-simulation with antenna. The chip area is 1.53mm2(1.29mm × 1.183mm).

摘要 I
Abstract III
誌謝 VI
目錄 VIII
表目錄 X
圖目錄 XI

第一章 緒論 1
1.1 研究背景與動機 1
1.2 鎖相迴路的實現方式 3
1.2.1 線性式鎖相迴路(Linear Phase Lock Loop) 3
1.2.2 電荷幫浦式鎖相迴路(Charge Pump Phase Lock Loop) 4
1.2.3 全數位式鎖相迴路(All Digital Phase Lock Loop) 4
1.2.4 軟體式鎖相迴路(Software Phase Lock Loop) 5
1.3 應用於IOP系統中之鎖相迴路選擇 6
1.4 論文概述 7

第二章 鎖相迴路基本觀念 9
2.1 鎖相迴路簡介 9
2.1.1 鎖相迴路的操作原理 9
2.1.2 線性模型 10
2.1.3 雜訊分析 14
2.2 鎖相迴路重要參數介紹 18
2.2.1 相位雜訊(Phase noise) 18
2.2.2 抖動(Jitter) 20
2.2.3 突波(spur) 22
2.2.4 優化指數(Figure of merit, FOM) 23
2.3 鎖相迴路構成方塊 25
2.3.1 相位頻率偵測器 25
2.3.2 電荷幫浦 27
2.3.3 迴路濾波器 31
2.3.4 壓控振盪器 32
2.3.5 除頻器 38
2.4 鎖相迴路系統設計及行為模擬 39
第三章 應用於IOP系統之鎖相迴路設計 43
3.1 相位頻率偵測器 43
3.2 電荷幫浦 48
3.3 迴路濾波器 53
3.4 壓控振盪器 60
3.5 除頻器 67
3.5.1 電流模式邏輯除二電路(Current Mode Logic,CML,divide-by-2) 68
3.5.2 多係數除頻器(Multi-Modulus Frequency Divider) 69
3.5.3 真實單相時脈除二電路(True Single Phase Clock,TSPC,divide-by-2) 72

第四章 應用於IOP系統之頻率電壓轉換器設計 73
4.1 相位頻率偵測器與電荷幫浦 74
4.2 迴路濾波器 76
4.3 壓控振盪器 77
4.4 單倍增益緩衝器 83

第五章 模擬與量測結果 85
5.1 鎖相迴路系統模擬與量測 85
5.1.1 2.2GHz鎖相迴路 86
5.1.2 5.8GHz鎖相迴路 95
5.2 頻率對電壓轉換器系統模擬與量測 101

第六章 結論與未來規劃 113
6.1 結論 113
6.2 未來規劃 114

附錄A 應用於IOP系統的感測器振盪電路設計 115
A.1感測器電路設計 115
A.2感測器電路模擬 121

參考文獻 127

[1]鄭煥騰, 前瞻無線眼壓監控模組之研究, 碩士, 電機與控制工程系所, 國立交通大學, 新竹市, 2008.
[2]邱繼崑, CMOS射頻頻率合成器電路之設計與製作, 碩士, 電機工程學研究所, 國立臺灣大學, 台北市, 2001.
[3]F. Gardner, Charge-Pump Phase-Lock Loops, IEEE Transactions on Communications, vol. 28, pp. 1849-1858, 1980.
[4]劉深淵, 楊清淵, “鎖相迴路, 滄海書局,2006.
[5]D. B. Leeson, A simple model of feedback oscillator noise spectrum, Proceedings of the IEEE, vol. 54, pp. 329-330, 1966.
[6]A. Hajimiri and T. H. Lee, A general theory of phase noise in electrical oscillators, IEEE Journal of Solid-State Circuits, vol. 33, pp. 179-194, 1998.
[7]D. Ham and A. Hajimiri, Concepts and methods in optimization of integrated LC VCOs, IEEE Journal of Solid-State Circuits, vol. 36, pp. 896-909, 2001.
[8]“Jitter in PLL-Based Systems: Cause, Effect, and Solution Cypress Semiconductor Corp, May 1995. Avaliable on: http://www.eetasia.com/ARTICLES/2001MAR/2001MAR23
[9]白安鵬, 半導體積體電路測試技術部落格, 訊號抖動的量測技術, 2010. Avaliable on: www.ictesting-tom.blogspot.tw
[10]D. Banerkee, PLL Performance, Simulation, and Design, National Semiconductor 1998.
[11]T. C. Steve Williams, Simulating PLL reference spurs, 2006. Avaliable on: www.rdeesign.com/mag/605RFD33.pdf
[12]H, Changhong, W, Xiushan, and W, Dan, A charge-pump circuit to restrain reference spurs in the PLL, IEEE 9th International Conference on ASIC (ASICON), pp. 1010-1013, 2011
[13]G. Xiang, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, pp. 117-121, 2009.
[14]B. Razavi, RF Microelectronics. New Jersey: Prentice Hall, 1998.
[15]A. Kral, F. Behbahani, and A. A. Abidi, RF-CMOS oscillators with switched tuning, in Custom Integrated Circuits Conference, Proceedings of the IEEE , pp. 555-558, 1998.
[16]Y. A. Eken and J. P. Uyemura, Multiple-GHz ring and LC VCOs in 0.18μm CMOS, in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 475-478,June 2004
[17]T. Miyazaki, M. Hashimoto, and H. Onodera, A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process, in Proceedings of the ASP-DAC. Asia and South Pacific, Design Automation Conference, pp. 545-546, 2004.
[18]A. L. , T. H. , Hajimiri, The Design of Low Noise Oscillators, (Kluwer Academic Press, Boston), 2002.
[19]葉詩涵, 應用於MB-OFDMUWB頻率合成器之鎖相迴路設計, 碩士, 電機工程學系碩博士班, 國立成功大學, 台南市, 2010.
[20]S. Mohamed, M. Ortmanns, and Y. Manoli, Design of current reuse CMOS LC-VCO, in Electronics, Circuits and Systems, 15th IEEE International Conference on ICECS. pp. 714-717, 2008.
[21]Y, Seok-Ju, S, So-Bong, C, Hyung-Chul, and L, Sang-Gug, A 1mW current-reuse CMOS differential LC-VCO with low phase noise, in Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. IEEE International, Vol. 1, pp. 540-616, 2005.
[22]O, Nam-Jin and L, Sang-Gug, Current reused LC VCOs, Microwave and Wireless Components Letters, IEEE, vol. 15, pp. 736-738, 2005.
[23]A. Hajimiri and T. H. Lee, Design issues in CMOS differential LC oscillators, IEEE Journal of Solid-State Circuits, vol. 34, pp. 717-724, 1999.
[24]L, Liang-Hung, H, Hsieh-Hung, and L, Yu-Te, A Wide Tuning-Range CMOS VCO With a Differential Tunable Active Inductor, IEEE Transactions on Microwave Theory and Techniques, vol. 54, pp. 3462-3468, 2006.
[25]G. von Buren, C. Kromer, F. Ellinger, A. Huber, M. Schmatz, and H. Jackel, A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS, in Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. IEEE International, pp. 2462-2471, 2006.
[26]T. S. Aytur and B. Razavi, A 2-GHz, 6-mW BiCMOS frequency synthesizer, IEEE Journal of Solid-State Circuits, vol. 30, pp. 1457-1462, 1995.
[27]W. Rhee, Design of high-performance CMOS charge pumps in phase-locked loops, in Circuits and Systems, Proceedings of the IEEE International Symposium on ISCAS . vol.2, pp. 545-548, 1999.
[28]L, Jae-Shin, K, Min-Sun, L, Shin-Il, and K, Suki, Charge pump with perfect current matching characteristics in phase-locked loops, Electronics Letters, vol. 36, pp. 1907-1908, 2000.
[29]S, Yuan, S, Liter, and S, Pengyu, Design of a High Performance Charge Pump Circuit for Low Voltage Phase-locked Loops, in Integrated Circuits, International Symposium on ISIC. pp. 271-274, 2007.
[30]C. T. Charles and D. J. Allstot, A buffered charge pump with zero charge sharing, in Circuits and Systems, IEEE International Symposium on ISCAS. pp. 2633-2636, 2008.
[31]H. Ningbing and L. Zhiqun, Design of high performance CMOS charge pump for phase-locked loops synthesizer, in Communications, 15th Asia-Pacific Conference on APCC. pp. 209-212, 2009.
[32]T, Geum-Young, H, Seok-Bong, K, Tae Young, C, Byoung Gun, and P, Seong Su, A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications, IEEE Journal of Solid-State Circuits, vol. 40, pp. 1671-1679, 2005.
[33]H, Zue-Der, K, Fong-Wei, W. Wen-Chieh, and W. Chung-Yu, A 1.5-V 3~10-GHz 0.18-μm CMOS frequency synthesizer for MB-OFDM UWB applications, in Microwave Symposium Digest, IEEE MTT-S International, pp. 229-232, 2008.
[34]M. Haase, V. Subramanian, Z. Tao, and A. Hamidian, Comparison of CMOS VCO Topologies, in Ph.D. Research in Microelectronics and Electronics Conference on (PRIME), pp. 1-4, 2010.
[35]G. De Astis, D. Cordeau, J. M. Paillot, and L. Dascalescu, A 5-GHz fully integrated full PMOS low-phase-noise LC VCO, IEEE Journal of Solid-State Circuits, vol. 40, pp. 2087-2091, 2005.
[36]W. Le, P. Upadhyaya, S. Pinping, Z. Yang, H. Deukhyoun, C. Yi-Jan Emery, and J. DongHo, A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor, in Circuits and Systems, IEEE International Symposium on ISCAS. Proceedings. 2006.
[37]V. B. Bhana, J. W. Lambrechts, and S. Sinha, The design of a 5 GHz VCO with phase noise performance analysis using MOSFET-based current sources, in Semiconductor Conference (CAS), International, pp. 335-338, 2011.
[38]Z, Wang, H, S. Savci, and N, S. Dogan, 1-V ultra-low-power CMOS LC VCO for UHF quadrature signal generation, in Circuits and Systems, IEEE International Symposium on ISCAS. Proceedings. 2006.
[39]T. H. Lee and A. Hajimiri, Oscillator phase noise: a tutorial, IEEE Journal of Solid-State Circuits, vol. 35, pp. 326-336, 2000.
[40]P. Heydari and R. Mohanavelu, Design of ultrahigh-speed low-voltage CMOS CML buffers and latches, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, pp. 1081-1093, 2004.
[41]N. Roberto, P. Enzo, P. Pierpaolo, and S. Luca, A Design Methodology for MOS Current-Mode Logic Frequency Dividers, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, pp. 245-254, 2007.
[42]李維傑, 適用於IEEE802.11a接收機之差異積分調變CMOS頻率合成器設計, 碩士, 電機資訊學院碩士在職專班, 國立交通大學, 新竹市, 2004.
[43]S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider, IEEE Journal of Solid-State Circuits, vol. 39, pp. 378-383, 2004.
[44]C, Chih-Wei and Y. J. E. Chen, A CMOS True Single-Phase-Clock Divider With Differential Outputs, Microwave and Wireless Components Letters, IEEE, vol. 19, pp. 813-815, 2009.
[45]M. S. c. , G. Jovanovi´c, Z. Stamenkovic, A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability,,2010.
[46]張佳陽, 鎖相迴路式頻率合成器之晶片研製與系統應用探討, 碩士, 電機工程學系碩士在職專班, 淡江大學, 新北市, 2003.
[47]M. S. C. , E. G. , JOVANOVI´C, Current starved delay element with symmetric load,, International Journal of Electronics, , Vol. 93, no. 3, pp. 167-175, 2006.
[48]O. T. C. Chen and R. R. B. Sheen, A power-efficient wide-range phase-locked loop, IEEE Journal of Solid-State Circuits, vol. 37, pp. 51-62, 2002.
[49]G, Xiang, E. A. M. Klumperink, G. Socci, M. Bohsali, and B, Nauta, Spur-reduction techniques for PLLs using sub-sampling phase detection, in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), IEEE International, pp. 474-475, 2010.
[50]K. J. Wang, A. Swaminathan, and I. Galton, Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2787-2797, 2008.
[51]L, Tai-Cheng and L, Wei-Liang, A Spur Suppression Technique for Phase-Locked Frequency Synthesizers, in Solid-State Circuits Conference, ISSCC. Digest of Technical Papers. IEEE International, pp. 2432-2441, 2006.
[52]Y. Chen, Z. Wang, and L. Zhang, A 5GHz 0.18μm CMOS technology PLL with a symmetry PFD, in Microwave and Millimeter Wave Technology, International Conference on ICMMT. pp. 562-565, 2008.
[53]W.-H. Chiu, Y.-H. Huang, and T.-H. Lin, A 5GHz phase-locked loop using dynamic phase-error compensation technique for fast settling in 0.18-μm CMOS, Symposium on VLSI Circuits, pp. 128-129, 2009.
[54]D, Ping-Yuan and K, Jean-Fu, A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 320-326, 2009.
[55]A. Liscidini, M. Tedeschi, and R. Castello, A 2.4 GHz 3.6mW 0.35mm2 Quadrature Front-End RX for ZigBee and WPAN Applications, in Solid-State Circuits Conference, ISSCC. Digest of Technical Papers. IEEE International, pp. 370-620, 2008.
[56]K. Vavelidis, I. Vassiliou, T. Georgantas, A. Yamanaka, S. Kavadias, G. Kamoulakos, C. Kapnistis, Y. Kokolakis, A. Kyranas, P. Merakos, I. Bouras, S. Bouras, S. Plevridis, and N. Haralabidis, A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18/spl mu/m CMOS RF transceiver for 802.11a/b/g wireless LAN, in Solid-State Circuits Conference, ESSCIRC. Proceedings of the 29th European, pp. 221-224, 2003.
[57]R. Ahola, A. Aktas, J. Wilson, K. R. Rao, F. Jonsson, I. Hyyrylainen, A. Brolin, T. Hakala, A. Friman, T. Makiniemi, J. Hanze, M. Sanden, D. Wallner, Y. Guo, T. Lagerstam, L. Noguer, T. Knuuttila, P. Olofsson, and M. Ismail, A single chip CMOS transceiver for 802.11 a/b/g WLANs, in Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. IEEE International, Vol.1, pp. 92-515, 2004.

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊