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研究生:郭家銘
研究生(外文):Chia-MingKuo
論文名稱:放寬回授路徑時間及使用運算放大器共用技術之低失真三角積分調變器設計
論文名稱(外文):Design of a Low-Distortion Sigma-Delta Modulator with Relaxed Feedback Path Timing and Operational Amplifier Sharing Technique
指導教授:劉濱達
指導教授(外文):Bin-Da Liu
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:99
中文關鍵詞:低失真三角積分調變器放寬回授路徑時間技術運算放大器共用技術資料加權平均演算法兼併式電容技術
外文關鍵詞:Low-distortion sigma-delta modulatorfeedback path relaxed timing techniqueoperational amplifier sharing techniquedata weighted averaging algorithmmerged capacitor switching technique
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本論文提出一種適用於無線通訊系統之低失真三角積分調變器,除了保有高解析度的特性外,更進一步拓寬頻寬與降低功率消耗。在本架構中,將調變器回授路徑的處理時間延長至時脈的半周期,以改善傳統低失真三角積分調變器在高速運作之下,量化器及動態元件匹配電路僅能運作在非重疊時脈時間的問題。另一方面,運算放大器是造成調變器功率消耗的主要原因,因此提出錯開三級積分器的積分時間的技巧,三級積分器的運算僅需一個運算放大器就能完成,大幅降低功耗。此外,為降低數位類比轉換器中電容的不匹配問題,於回授路徑中使用資料加權平均演算法,並在其電路實現中引入兼併式電容技術,藉此降低動態元件匹配電路的複雜度及面積的需求。
本電路使用90 nm一層多晶矽九層金屬線製程,設計出在供應電壓1.2 V、取樣頻率80 MHz、超取樣率16倍的設定下,訊號頻寬2.5 MHz的三階、四位元量化器之低失真三角積分調變器。由模擬結果得知,其有效位元數為12.93位元,訊雜比為79.62 dB,整體功率消耗為1.16 mW,FoM可低至29.66 fJ/ conversion。
This thesis presents the proposed low-distortion sigma-delta modulator which is suitable for the applications in wireless communication system. In addition to high resolution, extending the bandwidth and decreasing the power consumption are also goals of this design. The loop filter processes quantization error only in conventional low distortion sigma-delta modulator. However, the quantizer and dynamic element matching circuit are hard to accomplish in non-overlapping time interval for high speed applications. In order to mitigate the timing issue, the feedback path timing is relaxed to half cycle of clock period in the proposed architecture. On the other hand, the power consumed by operational amplifiers dominates the power consumption of overall modulator. The integration phases of three integrators have been staggered. Thus, the integrators in three stages are realized by only one operational amplifier. The power consumption is reduced greatly. Besides, the data weighted averaging algorithm adopts in dynamic element matching circuit to eliminate the effect of mismatch among capacitors in DAC. Merged capacitor switching technique is introduced into implementation of the proposed dynamic element matching circuit. Hence, its complexity and area are reduced.
The proposed low-distortion third-order sigma-delta modulator is simulated in 90-nm 1P9M 1.2-V CMOS process technology. The circuit is operated under 80 MHz clock rate and 2.5 MHz signal bandwidth with a supply voltage of 1.2V. Simulation results show that a 79.62-dB SNDR and 12.93-bit resolution are achieved with 1.16-mW total power consumption under 16-X oversampling ratio. FOM is 29.66 fJ/conversion.

Abstract (Chinese) i
Abstract (English) iii
Acknowledgement v
Table of Contents vii
List of Tables ix
List of Figures xi
Chapter 1 Introduction 1
1.1 Motivation and Background 1
1.2 Organization for the Thesis 2
Chapter 2 Fundamental of Analog-to-Digital Converter 5
2.1 Introduction of Analog-to-Digital Converter 5
2.1.1 Nyquist rate data converter 7
2.1.2 Oversampling data converter 8
2.2 Sigma-Delta Modulator 9
2.2.1 Oversampling technique 9
2.2.2 Noise-shaping technique 12
2.3 Sigma-Delta Modulator Topologies 14
2.3.1 Single loop topology 15
2.3.2 Multi-stage topology 17
2.3.3 Multi-bit quantization topology 19
2.4 Analysis of the Non-ideality in Sigma-Delta Modulator 20
2.4.1 Finite gain error 20
2.4.2 Integrator settling error 24
2.4.3 Noise in Switched-Capacitor Integrator 25
Chapter 3 Proposed Sigma-Delta Modulation Structure 27
3.1 Low-Distortion ΣΔ ADC 28
3.2 Prior Art of Improved Low-Distortion Sigma-Delta Modulator 31
3.2.1 Relaxed feedback path timing 31
3.2.2 Capacitive Input Feed-forward 32
3.2.3 Opamp sharing technique 34
3.3 Proposed Low-Distortion Sigma-Delta Modulator 35
3.3.1 Proposed architecture 35
3.3.2 Timing diagram 40
3.3.3 Matlab Simulation 41
3.4 Data weighted averaging (DWA) 47
Chapter 4 Implementation in Circuit Level 51
4.1 Loop Filter Design 52
4.1.1 Switched-capacitor integrator 52
4.1.2 Opamp Design 58
4.2 Quantizer Design 64
4.2.1 Asynchronous binary-search ADC 64
4.2.2 Comparator and reference ladder 66
4.2.3 Summary 68
4.3 DWA and DAC circuits design 70
4.3.1 Merged Capacitor Switching 70
4.3.2 DWA circuit design 72
4.4 Clock System 77
4.5 Simulation Results 80
Chapter 5 Conclusions and Future Work 87
5.1 Conclusions 87
5.2 Future Work 88
References 91
Publication and Award 97
Biography 99


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