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研究生:沈易律
研究生(外文):Yi-LyuShen
論文名稱:高效率三角積分調變器與簡化資料加權平均演算法之設計
論文名稱(外文):Design of a High-Efficient Delta-Sigma Modulator and Simplified Data Weighted Averaging Algorithm
指導教授:劉濱達
指導教授(外文):Bin-Da Liu
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:127
中文關鍵詞:三角積分調變器電荷幫浦式架構雜訊耦合技術低失真架構
外文關鍵詞:Delta-sigma modulatorCharge-pump basedNoise-couplingLow-distortion
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本論文提出一個創新之三角積分調變器架構與一種簡化資料加權平均演算法。此創新三角積分調變器使用電荷幫浦式三階低失真的架構設計,且加入雜訊耦合與放寬回授路徑時間之技術,以達到高解析度與低功率消耗之特色。在電路實現方面,此調變器內部之積分器使用共享運算放大器技術來更進一步地降低其功率消耗。另外一方面,本論文亦提出一種基於合併電容切換技術之數位類比轉換器的簡化資料加權平均演算法,相較於傳統資料加權平均演算法,此新式演算法可改善三角積分調變器之線性度與降低其電路實現之成本,並且達到低功率消耗之目的。此創新之三階四位元低失真三角積分調變器使用90 nm一層多晶矽九層金屬導線CMOS製程實現。模擬結果顯示,在80 MHz的取樣頻率與超取樣率為16倍的設定下,噪訊比最高可達到79.04 dB且其整體功率消耗僅為1.8 mW,經換算此電路之功率轉換效率為0.05 pJ/conversion,明顯優於目前已發表文獻之結果。
In this thesis, a proposed delta-sigma modulator and a simplified data weighted averaging algorithm are presented. The proposed delta-sigma modulator is designed in charge-pump based 3rd-order low-distortion topology with noise-coupling and relaxed feedback timing techniques to achieve high-resolution and low-power dissipation feature. In circuit implementation, the OPAMP-sharing technique is employed in the integrators to further reduce the power consumption. In addition, a simplified data weighted averaging (SDWA) algorithm based on merged-capacitor switching DAC is also presented in this thesis. Compared to the conventional DWA algorithm, the proposed SDWA algorithm improves the linearity of the modulator and reduces the cost of the SDWA circuit while maintaining the low-power consumption feature. This 3rd-order 4-bit low-distortion delta-sigma modulator is implemented by 90-nm 1P9M CMOS process. The simulation results show that the peak SNDR is 79.04 dB with sampling frequency of 80 MHz and oversampling ratio (OSR) of 16. The power dissipation is only 1.8 mW and the Figure-of-Merit is 0.05 pJ/conversion, which is much better than other published works.
Abstract (Chinese) i
Abstract (English) iii
Acknowledgement v
Table of Contents vii
List of Tables xi
List of Figures xiii
Chapter 1 Introduction 1
1.1 Motivation and Contribution 1
1.2 Organization for the Thesis 4
Chapter 2 Fundamental of Delta-Sigma Modulator 5
2.1 Introduction of Analog-to-Digital Converter 5
2.1.1 Nyquist-rate ADC 7
2.1.2 Oversampling-rate ADC 9
2.2 Delta-Sigma Modulator 10
2.2.1 Oversampling feature 10
2.2.2 Noise-shaping feature 14
Chapter 3 A Charge-Pump Based Low-Distortion 3rd-Order Delta-Sigma Modulator with Noise-Coupling Enhancement and Relaxed Feedback Timing Technique 21
3.1 Architecture Consideration 22
3.1.1 Consideration of conventional structures 22
3.1.2 The low-distortion architecture 23
3.1.3 The multi-bit quantizer configuration 25
3.1.4 The low-distortion architecture with relaxed feedback path timing 28
3.1.5 The noise-coupling enhancement technique 30
3.2 The Charge-Pump Based Switched-Capacitor Integrator 34
3.2.1 Introduction of the conventional charge-pump based switched-capacitor integrator 34
3.2.2 Introduction of the proposed charge-pump based switched-capacitor integrator 38
3.3 Circuit Implementation 42
3.3.1 Parasitic-insensitive charge-pump based integrator 42
3.3.2 Telescopic OPAMP adopted in the 1st and 2nd stages 47
3.3.3 4-bit cyclic-ADC quantizer with adopted active adder 55
3.3.4 Telescopic OPAMP adopted in the cyclic-ADC quantizer 62
3.3.5 The 1.5-bit and 2-bit sub-ADC adopted in cyclic ADC 66
3.3.6 Register and digital error correction circuit 69
3.3.7 Clock generator 73
3.3.8 Complete circuit diagram 75
3.4 Simulation Results and Measurement Environment 77
3.4.1 Simulation results 77
3.4.2 Layout consideration 83
3.4.3 Measurement environment 85
Chapter 4 Simplified Data Weighted Averaging Algorithm Based on Merged-Capacitor Switching DAC Array 87
4.1 Introduction of Conventional Data Weighted Averaging Algorithm 88
4.2 Introduction of Proposed DAC with Merged-Capacitor Switching 90
4.3 Simplified Data Weighted Averaging Algorithm Based on Merged- Capacitor Switching DAC Array 94
4.4 Circuit Implementation 97
4.4.1 Two’s complement correction circuit 99
4.4.2 Point generator and decoder 101
4.4.3 Binary-to-thermometer code converter 103
4.4.4 Barrel shifter 105
4.4.5 Selecting control-signals logic 107
4.5 Microphotograph and Simulation Results 108
4.5.1 Microphotograph and floor-plan 108
4.5.2 Simulation results 109
Chapter 5 Conclusions and Future Work 113
5.1 Conclusions 113
5.2 Future Work 115
References 117
Patent and Awards 125
Biography 127
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