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研究生:黃嘉俊
研究生(外文):Chia-ChunHuang
論文名稱:使用無負載延伸計數技術之增量型類比至數位轉換器設計
論文名稱(外文):Design of an Incremental Analog-to-Digital Converter with Loading-Free Extended Counting Technique
指導教授:劉濱達林家民林家民引用關係
指導教授(外文):Bin-Da LiuBin-Da Liu
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:71
中文關鍵詞:無負載延伸計數技術增量型三角積分調變器連續漸進式轉換器類比至數位轉換器
外文關鍵詞:Loading-free extended counting architectureincremental sigma-delta modulatorsuccessive approximation registeranalog-to-digital converter
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  • 被引用被引用:0
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  • 下載下載:23
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本論文提出基於增量型類比至數位轉換器之無負載延伸計數架構,並結合具有高使用效率特性的連續漸進式類比至數位轉換器。本論文設計解析度為十二位元之轉換器,其中包括解析最大有效位元的充電幫浦增量型轉換器和解析最小有效位元的同步連續漸進式轉換器,而且無需額外校正機制。此轉換電路使用連續漸進式轉換器來完成延伸轉換,透過所提出的無負載延伸計數架構,增量型轉換器中的積分器並不需要連續漸進式轉換器的電容陣列來作為儲存殘值的負載,如此即能放寬放大器所需要的規格。增量型轉換器及連續漸進式轉換器採用平行方式處理,可減少電路轉換時間。電路以TSMC 0.18-μm 1P6M CMOS製程來模擬設計,在訊號頻寬為2 kHz和供應電壓為1.8 V環境下,此轉換器之SNDR可達到69.38 dB,功率消耗僅為23.07 μW。
In this thesis, the loading-free extended counting architecture based on incremental ADC that uses SAR modulator to take an advantage of power efficiency is proposed. This work adopts a charge-pump incremental ADC to convert the first 5-bit MSB and a synchronous SAR modulator to convert the last 7-bit LSB, and thus totally 12-bit resolution can be obtained without calibration. The SAR ADC is used to complete the extended conversion, but with the proposed architecture the residual error integrator of the counting converter is not loaded by the DAC capacitor array of SAR modulator, which means the operational amplifier design can be relaxed. Since the used incremental ADC and SAR modulator are operated in parallel, total conversion time of this ADC can be reduced. The proposed converter is implemented in TSMC 0.18-μm 1P6M CMOS technology. Under 2-kHz input signal bandwidth and 1.8-V power supply, the simulated peak SNDR of 69.38 dB is achieved with only 23.07-μW power consumption.
Abstract (Chinese) i
Abstract (English) iii
Acknowledgement v
Table of Contents vii
List of Figures xi
List of Tables xiii
Chapter 1 Introduction 1
1.1 Motivation and Introduction 1
1.2 Research Procedure 4
1.3 Thesis Outline 4
Chapter 2 Fundamental Concepts of Analog-to-Digital Converter 7
2.1 Analog-to-Digital Conversion 7
2.1.1 Quantization error 8
2.1.2 Nyquist-rate conversion 9
2.1.3 Oversampling conversion 10
2.2 Sigma-Delta Modulators 10
2.3 Incremental Sigma-Delta Modulators 12
2.4 Successive Approximation Register Modulators 15
2.5 Extended Counting Technique 17
2.6 Summary 20
Chapter 3 Design of an Incremental ADC with Loading-Free Extended Counting Architecture 21
3.1 Sample-Hold Amplifier 22
3.1.1 Single-to-differential sample-hold amplifier 23
3.1.2 Bootstrapped switch 24
3.1.3 Simulation results 25
3.2 Incremental ADC with charge-pump technique 27
3.2.1 Charge-pump technique 27
3.2.2 Decimation filter 30
3.2.3 Simulation results 30
3.3 Successive Approximation Register ADC 32
3.3.1 Capacitor array 33
3.3.2 DAC control logic 34
3.3.3 Timing control logic 35
3.3.4 Simulation results 36
3.4 Loading-Free Extended Counting Architecture 38
3.4.1 Extended counting with loading-free 39
3.4.2 Parallel operation 40
3.5 Summary 42
Chapter 4 Experimental Results and Comparison 43
4.1 Circuit Implementation 44
4.1.1 Two-stage operational amplifier with Miller compensation 44
4.1.2 Dynamic Comparator 49
4.1.3 Controlling clock phases 51
4.2 Simulation Results 52
4.2.1 Layout 52
4.2.2 Simulation results 54
4.2.3 Comparison and discussion 57
4.3 Measurement Results 58
4.3.1 Measurement environment 59
4.3.2 Measurement results and discussion 61
Chapter 5 Conclusions and Future Work 63
5.1 Conclusions 63
5.2 Future Work 64
References 67

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