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研究生:林錫宏
研究生(外文):Xi-HongLin
論文名稱:適用於分散式運算之離散傅立葉轉換設計
論文名稱(外文):The Efficient Hardware Design for Discrete Fourier Transform Using Distributed Arithmetic
指導教授:雷曉方
指導教授(外文):Sheau-Fang Lei
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:117
中文關鍵詞:離散傅立葉轉換分散式運算質數非質數現場可程式化邏輯閘陣列
外文關鍵詞:DFTdistributed arithmeticprimenon-primeFPGA
相關次數:
  • 被引用被引用:0
  • 點閱點閱:153
  • 評分評分:
  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
在數位訊號處理(DSP or digital signal processing)的領域中,離散傅立葉轉換(DFT or discrete Fourier transform)扮演著相當關鍵的角色,在目前某些通訊系統的規格中,DFT傳輸點數為非2的冪次方,因此需要提出可以適用於此種要求的設計。在本論文中,作者提出適合分散式運算的演算法與硬體架構來計算DFT,這是一種使用唯讀記憶體(ROM or read only memory)與移位累加器的設計,此種設計不需要使用乘法器,因此如何有效的去減小ROM size為主要的考量。作者分別針對質數點數(prime length)與非質數點數(non-prime length) DFT提出適用於分散式運算的演算法與硬體架構,相較於目前已經存在的方法,作者提出的計算質數點數與非質數點數DFT的方法,分別節省了66%、97% ROM size與50%、55%的加法器數量。此外,在硬體架構上,相較於其他的電路設計,在本論文中電路的關鍵路徑是最短的,可以預期的是電路可操作的速度為最快。
In digital signal processing (DSP), the discrete Fourier transform (DFT) is crucial. These days, the transform length of DFT is not power of two in some specification of communication system, so we need to find a way to meet this requirement. In this thesis, the author has proposed algorithm and hardware architecture suitable for DA to calculate DFT, this is the design using ROM and shift adder, but there is no multiplier. The author has proposed algorithm and hardware suitable for DA to calculate prime length DFT and non-prime length DFT. Compared with existing method, proposed method has improved by 66% and 97% in ROM size for prime length and non-prime length DFT, respectively; in addition, proposed method has improved by 50% and 55% in number of adder for prime length and non-prime length DFT, respectively. Moreover, the critical path of proposed circuit is minimum. Thus it can be expected that clock speed of proposed circuit is maximum.
摘要 I
Abstract II
誌謝 III
目錄 IV
表目錄 VI
圖目錄 VIII
第 1 章 緒論 1
1.1 研究背景與動機 1
1.2 論文組織 2
第 2 章 文獻回顧 3
2.1 前言 3
2.2 分散式運算[15-19] 3
2.3 Siu et al.’s 演算法[12] 6
2.4 Chen et al.’s 演算法[14] 11
2.4.1 GDA approach for cyclic convolution 11
2.4.2 BGDA realization on long length cyclic convolution 13
2.4.3 GDA方法應用在1-D DFT 17
第 3 章 所提出之DA-BASED DFT演算法及其架構 27
3.1 前言 27
3.2 Prime length 27
3.2.1 演算法 27
3.2.2 硬體架構 41
3.3 Non-prime length 48
3.3.1 演算法 48
3.3.2 硬體架構 55
第 4 章 模擬與比較 69
4.1 前言 69
4.2 比較 69
4.2.1 硬體資源 69
4.2.2 關鍵路徑 77
4.3 模擬 79
4.3.1 ASIC design flow 79
4.3.2 FPGA 104
第 5 章 結論 113
參考文獻 115
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