臺灣博碩士論文加值系統

本論文所研究的元件為暫態電壓抑制器(Transient Voltage Suppressor, TVS)，暫態電壓抑制器為現今靜電防護元件的發展主流。首先我們使用Silvaco TCAD模擬無磊晶層雙向式TVS，經由TCAD的模擬結果觀察、分析在改變摻雜濃度與改變光罩距離時元件的電性變化。使用Tanner L-Edit做光罩設計，並對實際下線的元件做量測結果討論，比較軟體模擬與實際下線元件的差異性。最後利用Hspice電路分析模擬軟體比較TVS陣列電路與一般二極體陣列電路在靜電防護效能上的差異性。

The device in this thesis is Transient Voltage Suppressor(TVS). TVS is the mainstream of today's ESD protection devices. First, we simulated Non-Epitaxy layer bi-directional TVS by Silvaco TCAD. In the experiment of TCAD simulation, we observed and analyzed the variation of electrical characteristics when the doping concentration and the mask distance were changed.

This experiment also used Tanner L-edit designing layout and measurement results and discussions of layout devices to compare software simulation with the actual layout devices. Finally, we used Hspice circuit simulation software to compare TVS array with general diodes array to find out the differences in the performance of electrostatic protection.

摘要 I
Abstract II
致謝 III
目錄 IV
表目錄 VI
圖目錄 VII
第一章 緒論 1
1.1 前言 1
1.2 研究動機與目的 2
1.3 章節介紹 3
第二章 靜電放電的簡介與規範 4
2.1 靜電放電簡介 4
2.2 靜電放電模型簡介 7
2.3 IEC-61000-4-2 靜電放電測試規範介紹 11
2.4 靜電保護元件的應用與選擇標準 14
第三章 暫態電壓抑制器的介紹與特性探討 16
3.1 靜電放電保護元件之保護動作原理 16
3.2 暫態電壓抑制器的相關參數 17
3.3 暫態電壓抑制器的種類 19
3.3.1 壓敏電阻 19
3.3.2 陶瓷電容 21
3.3.3 齊納二極體 22
3.3.4 暫態電壓抑制器 24
3.4 P-N接面原理探討 27
3.4.1 P-N接面二極體 27
3.4.2 P-N接面原理 30
3.4.3 接面崩潰現象探討 34
3.4.4 光罩佈局討論 39
3.5 無磊晶層雙向式TVS 43
第四章 元件模擬與量測 47
4.1 實驗流程 47
4.2 元件模擬 49
4.2.1 摻雜濃度變化討論 49
4.2.2 光罩距離變化討論 63
4.3 元件量測 76
4.3.1 元件量測 76
4.3.2 量測結果討論 78
4.4 靜電放電SPICE模擬 80
4.4.1 模擬簡介 80
4.4.2 IEC 61000−4−2模擬 90
4.4.3 靜電放電工業測試模型之電路模擬討論 94
第五章 結論 101
5.1 結論 101
5.2 未來方向 102
第六章 參考文獻 103

1. D.D.Ward, “Electrostaic discharge. IEE Seminar on EMC Design: p. pp.4/1-4/8.
2. Rhoades, W.T. “ Avoidance of ESD effects. in Electromagnetic Compatibility, 1988. Symposium Record., IEEE 1988 International Symposium on. 1988.
3. 李介文, “靜電放電防護-奈米元件未知的挑戰. 國研科技. 8: p. pp.39-42.
4. http://www.esd-china.com/big/papers/paper.htm.
5. R.Paul Clayton., “ Introduce to electromagnetic compatibility, John Wiley ＆ Sons Inc, chapter 12.
6. Ker, M.D., J.J. Peng, and H.C. Jiang. “ ESD test methods on integrated circuits: an overview. 2001. IEEE.
7. Walraven, JA,Soden, JM,Cole, EI,Tanner, DM,Anderson, RE,. “ Human Body Model, Machine Model, and Charge Device Model ESD testing of surface micromachined microelectromechanical systems (MEMS) . 2001. IEEE.
8. ESDA/JEDEC JESD22-A114F, “ Electrostatic discharge (ESD) sensitivity t esting-human body model- component level. JEDEC, 2010.
9. ESD Association Standard STM5.2-1999, “ For electrostatic discharge sensitivity testing - Machine Model (MM) - component level. ESD Association, 1999.
10. SD Association Standard STM5.3.1-1999, “For electrostatic discharge sensitivity testing - Charged Device Model (CDM) - component level. ESD Association, 1999.
11. Amerasekera, E. Ajith/ Duvvury, Charvaka/ Anderson, Warren/ Gieser, Horst/ Amerasekera, Ajith, Charvaka/ Anderson, Warren/ Gieser, Horst/ Amerasekera, Ajith, “ESD in Silicon Integrated Circuits ,John Wiley ＆ Sons, 2002.
12. http://www.ics.ee.nctu.edu.tw/~mdker/ESD/index/index2.html.
13. http://solutions.3m.com.tw/wps/portal/3M/zh_TW/ESD/home /ESD_TW/whatIs/.
14. IEC 61000-4-2 Standard, “ EMC – Part 4-2: Testing and Measurement Techniques – Electrostatic Discharge Immunity Test. IEC, 2008.
15. Microelectronics test method standard MIL-STD-883D method 3015.7
, “Electrostatic discharge sensitivity classification. US Department of Defense, 1991.
16. IEC 61000-4-2, Electromagnetic Compatibility (EMC)– part 4-2, “ Testing and measurement techniques- Electrostatic discharge immunity test. edition 1.1 edMay 1999.
17. 林居敬, “深入探討靜電保護的重要性.
18. King, Y.C. ,Yu, B. ,Pohlman, J. ,Hu, C., “Punchthrough diode as the transient voltage suppressor for low-voltage electronics. Electron Devices, IEEE Transactions on, 1996. 43(11): p. 2037-2040.
19. Obreja, V.V.N. “Capabilities and limitations of semiconductor surge voltage suppressors. 1999. IEEE.
20. Interpretation of Datasheet Parameters for ESD
Devices: ON-Semiconductor.
21. J. Lin, C.K., “Multilayer ZnO Varistor,US Patent # 5,369,390, 1994.
22. Rabde, V.P. “ Metal oxide varistors as surge suppressors. in Electromagnetic Interference and Compatibility '97. Proceedings of the International Conference on. 1997.
23. Rostamzadeh, C., H. Dadgostar, and F. Canavero. “ Electrostatic discharge analysis of multi layer ceramic capacitors. 2009. IEEE.
24. Yu, B. ,Hu, C. ,King, Y.C. ,Pohlman, J.T. ,Trivedi, R. , “Low-voltage punch-through transient suppressor employing a dual-base structure, 1999, US Patent 5,880,511.
25. Luh, L., J. Choma Jr, and J. Draper. “A Zener-diode-activated ESD protection circuit for sub-micron CMOS processes. 2000. IEEE.
26. http://www.ce-mag.com/archive/01/Spring/Lee.html.
27. Lin, K. ,Chen, Z. ,Chuang, C. ,Jiang, R.H., “VERTICAL TRANSIENT VOLTAGE SUPPRESSORS, 2012, US Patent 20,120,025,350.
28. 陳家承, “低電容背對背二極體式暫態電壓抑制器之設計. 清華大學電子工程研究所碩士論文, 2009.
29. 劉傳璽、陳進來, “半導體元件物理與製程－理論與實務,2006: 五南.
30. D.A.Neamen, “Semiconductor physics and devices, The McGraw-Hill Companies Inc.,Chapter7,8. , 2003
31. www.taiwan921.lib.ntu.edu.tw/mypdf/veee03.pdf.
32. http://sun.cis.scu.edu.tw/~lab/knowledge/c.htm.
33. Dai, S.H. ,Peng, J.J. ,Chen, C.C. ,Lin, C.J. ,King, Y.C., “Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor. Japanese Journal of Applied Physics, 2010. 49(4).
34. 黃崇偉, “高效能靜電防護二極體之研發與探討. 臺南大學電機工程研究所碩士班論文, 2011.
35. 李博明‧唐經洲, “VLSI 設計概論/實論, 2011.
36. http://www.macronix.com/.
37. http://www.onsemi.cn/.
38. 邱冠銘, “電子裝置靜電放電測試的模擬分析與實驗. 中山大學通訊工程研究所碩士班論文, 2004.
39. 詹奕倫, “高速數位系統中靜電放電保護元件之研究. 中山大學通訊工程研究所碩士班論文, 2005.