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研究生:吳俊勳
研究生(外文):Chun-HsunWu
論文名稱:具備高速暫態響應之無輸出電容型低壓降電壓調節器
論文名稱(外文):Fast Transient Output-Capacitorless Low-Dropout Voltage Regulator
指導教授:張簡樂仁
指導教授(外文):Le-Ren Chang-Chien
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:81
中文關鍵詞:電源管理IC電源轉換器低壓降電壓調節器負載暫態響應參考電壓追蹤響應
外文關鍵詞:Power management ICPower convertersLow-dropout voltage regulatorLoad transient responseReference tracking response
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攜帶型電子產品的多元發展,使得晶片系統電源轉換器的角色越來越重要,本論文首先簡介三種常用之晶片系統電源轉換器,接著介紹晶片電源常用且重要性越來越高的低壓降電壓調節器(low dropout voltage regulator, LDO),分析其基本工作原理、交流小信號模型以及暫態響應,並介紹近期LDO發展的重要特性。文中分析影響負載暫態響應及參考電壓追蹤響應的關鍵因素,靜態電流。高靜態電流雖然能使LDO擁有良好的暫態響應,卻會影響到電壓調節器的整體效率。針對此議題,本文首先提出瞬間靜態電流提升電路及多路徑巢狀米勒補償之新型LDO,其特點包含低工作電壓、低靜態電流、快速暫態響應、無輸出電容以及具有動態偏壓的特性,此電路的理論分析、模擬結果以及晶片實測結果也都在文中呈現。瞬間靜態電流提升電路雖然具有動態偏壓及良好暫態響應的效果,但電路穩態時因為無自動斷電之功能,因此也會造成多餘的功耗,為了改善此一缺點,本文另提出全靜態電流提升電路。
全靜態電流提升電路在負載暫態響應時,能瞬間將靜態電流值提升至最大,以完成快速的暫態響應,並具備自動斷電之功能,以達成最低之耗能。由負載暫態響應實測結果顯示,在供應電壓1.5V時預設輸出1.3V的狀況下,與無動態偏壓的電壓調節器相較,在負載變動於300ns內變動50mA時其輸出電壓壓降改善了62%,電壓回復時間小於0.5μs。
除了負載暫態響應之外,另一個全靜態電流提升電路也可達成的功能,是改善其參考電壓追蹤響應。參考電壓追蹤響應可應用在植入型生醫系統,因其需要動態電壓與頻率調節(dynamic voltage and frequency scaling, DVFS)來節省功率。使參考電壓追蹤響應最佳化的關鍵因素,也為靜態電流Iq。本文所提出之全靜態電流提升電路在參考電壓變動時,也能將靜態電流瞬間提升至最大,以加快參考電壓追蹤的響應,因此其電路也可以用來改善參考電壓追蹤響應之速度。由此可見藉由所提出之電路,可容易地實現一個低工作電壓、低靜態電流、無輸出電容、快速負載及參考電壓追蹤響應的低壓降電壓調節器。

With the versatile developing trend of the portable electronic devices, the role of on-chip power converters is becoming more and more important for the integrated circuits (ICs). This dissertation first introduces three types of commonly used on-chip power converters. Following that, the topic focuses on the low-dropout voltage regulator (LDO) due to its generality and significance in the IC power supply. LDO’s basic working principle, small signal model, as well as load transient response are comprehensively illustrated. Major issues of the recent researches including the low supply voltage, low quiescent current, fast load transient response and output-capacitorless structure are discussed. Specifically, influence of the quiescent current of the OPA on LDO’s load transient and reference tracking is then reviewed in detail. To achieve fast transient but keep quiescent current as low as possible for improving the power efficiency, this dissertation proposes two dynamic bias approaches to enhance the transient response of the LDO. The first proposed circuit is called transient quiescent current booster (TQCB). Embedding a TQCB within the OPA of a LDO, theoretical analysis and test results have shown its effectiveness in the fast transient performance. However, this design does not reach the optimal power efficiency because the TQCB circuit always consumes a branch current either the LDO is working in standby or active mode.
To design a faster transient response and more power-efficient LDO, a full quiescent current enhancement (FQCE) circuit which possesses the automatic shut-off function is proposed afterward. Testing results show that the voltage spike is reduced about 62% compared with the LDO without the proposed circuit in response to 50mA/300ns load change. Under such a load change, the voltage recovery time of the LDO is less than 0.5μs and the stability is guaranteed.
In addition to the load transient response, the other important feature that the FQCE circuit can do is to facilitate the reference tracking speed. Reference tracking is generally required in the bio-implantable medical devices to achieve dynamic voltage and frequency scaling (DVFS) for saving more power. The key factor for optimizing the reference tracking is determined by the quiescent current Iq as well. Therefore, the FQCE circuit is also suitable to the reference tracking issue. With the FQCE circuit, a fast transient output-capaciotrless LDO working at low supply voltage with high power efficiency could be easily implemented in various IC power applications.
Chapter 1 Introduction 1
1.1 Review of Research Background 1
1.2 Motivations 5
1.3 Dissertation Organization 6
Chapter 2 Basic Concept of the Conventional Low-Dropout Regulator 8
2.1 Working Principles of the Conventional LDOs 8
2.2 Terms and Definitions 9
2.2.1 Dropout Voltage 9
2.2.2 Efficiency 10
2.2.3 Load Regulation 11
2.2.4 Line Regulation 11
2.2.5 Power Supply Rejection Ratio 11
2.2 Small-Signal Analysis of the Conventional LDOs 12
2.3 Load Transient Response of the Conventional LDOs 16
2.4 Design Issues of the Newly Developed LDOs 17
Chapter 3 Quiescent Current Related Issues on the LDOs 20
3.1 Quiescent Current 20
3.2 Quiescent Current Effect on Load Transient of the Output-Capacitorless LDO 21
3.3 Transient Quiescent Current Enhancement Technique on the LDOs 22
Chapter 4 Transient Response Enhancement Using the Multipath Nested Miller Compensation with a Transient Quiescent Current Booster 25
4.1 LDO with Nested Miller Compensation 25
4.2 LDO with the Multipath Nested Miller Compensation (MNMC) 27
4.3 Time Domain Analysis of the TQCB Supplemented LDO 29
4.4 Small Signal Analysis of the MNMC Based LDO 31
4.4.1 Derivation of the LDO Model in Connection with the Equivalent Parallel LCR for the Power Line 33
4.4.2 Derivation of the LDO Model with the Resistor in Parallel with a Capacitor-Inductor in Series for the Power Line 37
4.5 Real Implementation and Test Results of the TQCB Based LDO 44
4.6 Summary 47
Chapter 5 Transient Response Enhancement Using the Full Quiescent Current Enhancement Circuit 49
5.1 Concept of Dynamic Biasing 49
5.2 Full Quiescent Current Enhancement Circuit 52
5.2.1 AC Analysis of the LDO with the Proposed FQCE Circuit 56
5.2.2 Real Implementation and Test Results of the Load Transient 61
5.3 Full Quiescent Current Enhancement Circuit for Reference Tracking 63
5.3.1 Reference Tracking in Output-Capacitorless LDO 64
5.3.2 FQCE Circuit for the Reference Tracking in the Output-Capacitorless LDO 65
5.3.3 Simulated and Real Test Results of the Reference Tracking 67
5.4 Summary 69
Chapter 6 Conclusion and Future Work 71
Reference 74

[1]M. Hiraki, T. Ito, A. Fujiwara, T. Ohashi, T. Hamano, T. Noda, A 63-μW standby power microcontroller with on-chip hybrid regulator scheme, IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 605-611, May 2002.
[2]M. H. Rashid, Power electronics: circuits, devices, and applications, Prentice-Hall International, Inc
[3]W. R. Liou, M. L. Yeh, and Y. L. Kuo, A high efficiency dual-mode buck converter IC for portable applications, IEEE Trans. Power Electron., vol. 23, pp. 667-677, Mar 2008
[4]K.-H. Chen, C.-C. Chien, C.-H. Hsu, and L.-R. Huang, Optimum power-saving method for power MOSFET width of DC-DC converters, IET Proc. Circuits, Devices Syst., vol. 1, no. 1, pp. 57–62, Feb. 2007.
[5]T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama, Variable supply-voltage scheme for low-power high-speed CMOS digital design, IEEE J. Solid-State Circuits, vol. 33, pp. 454-462, Mar 1998.
[6]M. Siu, P. K. T. Mok, K. N. Leung, Y. H. Lam, and W. H. Ki, A voltage-mode PWM buck regulator with end-point prediction, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 294-298, Apr 2006.
[7]K. H. Chen, H. W. Huang, and S. Y. Kuo, Fast-transient dc-dc converter with on-chip compensated error amplifier, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, pp. 1150-1154, Dec 2007.
[8]C. F. Lee and P. K. T. Mok, A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique, IEEE J. Solid-State Circuits, vol. 39, pp. 3-14, Jan 2004.
[9]D. S. Ma, W. H. Ki, and C. Y. Tsui, An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction, IEEE J. Solid-State Circuits, vol. 39, pp. 140-149, Jan 2004.
[10]F. Su, W. H. Ki, and C. Y. Tsui, Ultra fast fixed-frequency hysteretic buck converter with maximum charging current control and adaptive delay compensation for DVS applications, IEEE J. Solid-State Circuits, vol. 43, pp. 815-822, Apr 2008.
[11]G. Y. Wei and M. Horowitz, A fully digital, energy-efficient, adaptive power-supply regulator, IEEE J. Solid-State Circuits, vol. 34, pp. 520-528, Apr 1999.
[12]B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, High-frequency digital PWM controller IC for DC-DC converters, IEEE Trans. Power Electron., vol. 18, pp. 438-446, Jan 2003.
[13]T. Kuroda et al., Variable supply-voltage scheme for low-power high-speed CMOS digital design, IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 454–462, Mar. 1998.
[14]P. Y. Wu, P. K. T. Mok, A monolithic buck converter with near-optimum reference tracking response using adaptive-output-feedback, IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2441–2450, Nov. 2007.
[15]V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor, IEEE Trans. VLSI Syst., vol. 11, pp. 514–522, June 2003.
[16]H. Chug, A. Ioinovici, Inductorless DC-to-DC converter with high power density, IEEE Trans. Ind. Electron., vol. 41, no. 2, pp. 208–215, Apr. 1994.
[17]A. Ioinovici, Switched-capacitor power electronics circuits, IEEE Circuits and Syst. Magazine, vol. 1, no. 3, pp. 37–42, 2001.
[18]C. Jia, H. Chen, M. Liu, C. Zhang, Z. Wang, Integrated power management circuit for piezoelectronic generator in wireless monitoring system of orthopaedic implants, IET Proc. Circuits, Devices Syst., vol. 2, no. 6, pp. 485–494, Dec. 2008.
[19]B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, 2001.
[20]P. R. Gray and R. G. Meyer, Analysis and design of analog integrated circuits New York: John Wiley & Sons, Inc., 2000
[21]G. A. Rincon-Mora, P. E. Allen, A low-voltage, low quiescent current, low drop-out regulator, IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36–44, Jan. 1998.
[22]G. A. Rincon-Mora, P. E. Allen, Optimized frequency-shaping circuit topologies for LDOs, IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 45, no. 6, pp. 703–708, Jun. 1998.
[23]K. N. Leung, P. K. T. Mok, A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691–1702, Oct. 2003.
[24]W. J. Huang and S. I. Liu, Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array, IET Circuits Devices & Syst., vol. 2, no. 3, pp. 306-316, Jun. 2008.
[25]R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, Full on-chip CMOS low-dropout voltage regulator, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, pp. 1879-1890, Sep 2007.
[26]G. Giustolisi and G. Palumbo, Dynamic-biased capacitor-free NMOS LDO voltage regulator, Electronics Letters, vol. 45, pp. 1140-U56, Oct 2009.
[27]E. N. Y. Ho and P. K. T. Mok, A capacitor-less cmos active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, pp. 80-84, Feb. 2010.
[28]B. S. Lee, Understanding the terms and definitions of LDO voltage regulators, Application Report, Texas Instruments Inc. Oct. 1999.
[29]G. A. Rincon-Mora, Current efficient, low voltage, low dropout regulators, Georgia Institute of Technology, Ph. D Dissertation 1996.
[30]C. Simpson, Linear and switching voltage regulator fundamentals, Application Report, National Semiconductor Inc.
[31]B. S. Lee, Technical review of low dropout voltage regulator operation and performance, Application Report, Texas Instruments Inc. Aug. 1999.
[32]J. C. Teel, Understanding power supply ripple rejection in linear regulators, Application Report, Texas Instruments Inc. 2Q. 2005
[33]E. Rogers, Stability analysis of low-dropout linear regulators with a PMOS pass element, Application Report, Texas Instruments Inc. Aug. 1999.
[34]B. S. Lee, Understanding the stable range of equivalent series resistance of an LDO regulator, Application Report, Texas Instruments Inc. Nov. 1999.
[35]B. M. King, Understanding the load-transient response of LDOs, Application Report, Texas Instruments Inc. Nov. 2000.
[36]T. Y. Man, K. N. Leung, C. Y. Leung, P. K. T. Mok, and M. Chan, Development of single-transistor-control LDO based on flipped voltage follower for SoC, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, pp. 1392-1401, Jun 2008.
[37]S. K. Lau, P. K. T. Mok, and K. N. Leung, A low-dropout regulator for SoC with Q-reduction, IEEE J. Solid-State Circuits, vol. 42, pp. 658-664, Mar 2007.
[38]T. Y. Man, P. K. T. Mok, and M. Chan, A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, pp. 755-759, Sep 2007.
[39]A. D. Grasso, D. Marano, G. Palumbo, and S. Pennisi, Analytical comparison of reversed nested Miller frequency compensation techniques, International Journal of Circuit Theory and Applications, vol. 38, no. 7, pp. 709-737, Sept. 2010.
[40]C. Jia, H. Chen, M. Liu, C. Zhang, and Z. Wang, Integrated power management circuit for piezoelectronic generator in wireless monitoring system of orthopaedic implants, IET Circuits Devices & Syst., vol. 2, no. 6, pp. 485-494, Dec. 2008.
[41]C. K. Chava and J. Silva-Martinez, A frequency compensation scheme for LDO voltage regulators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, pp. 1041-1050, Jun 2004.
[42]A. Garimella, M. W. Rashid, and P. M. Furth, Reverse nested Miller compensation using current buffers in a three-stage LDO, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 4, pp. 250-254, Apr. 2010.
[43]M. El-Nozahi, A. Amer, J. Torres, K. Entesari, and E. Sanchez-Sinencio, High PSR low drop-out regulator with feed-forward ripple cancellation technique, IEEE J. Solid-State Circuits, vol. 45, pp. 565-577, Mar. 2010.
[44]S. Yeung, J. Guo, and K. N. Leung, 25 mA LDO with-63 dB PSRR at 30 MHz for WiMAX, Electronics Letters, vol. 46, pp. 1080-U57, Jul. 2010.
[45]S. Heng and C. K. Pham, A low-power high-PSRR low-dropout regulator with bulk-gate controlled circuit, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, pp. 245-249, Apr. 2010.
[46]A. P. Patel and G. A. Rincon-Mora, High power-supply-rejection (psr) current-mode low-dropout (LDO) regulator, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, pp. 868-873, Nov. 2010.
[47]P. Y. Or and K. N. Leung, A fast-transient low-dropout regulator with load-tracking impedance adjustment and loop-gain boosting technique, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, pp. 757-761, Oct. 2010.
[48]M. Al-Shyoukh, H. Lee, and R. Perez, A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation, IEEE J. Solid-State Circuits, vol. 42, pp. 1732-1742, Aug 2007.
[49]P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar, Area-efficient linear regulator with ultra-fast load regulation, IEEE J. Solid-State Circuits, vol. 40, pp. 933-940, Apr 2005.
[50]H. Lee, P. K. T. Mok, and K. N. Leung, Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, pp. 563-567, Sep 2005.
[51]H. C. Lin, H. H. Wu, and T. Y. Chang, An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, pp. 853-857, Sep 2008.
[52]C. H. Lin, K. H. Chen, and H. W. Huang, Low-dropout regulators with adaptive reference control and dynamic push-pull techniques for enhancing transient performance, IEEE Trans. Power Electron., vol. 24, pp. 1016-1022, Mar 2009.
[53]M. Ho, K. N. Leung, and K. L. Mak, A low-power fast-transient 90-nm low-dropout regulator with multiple small-gain stages, IEEE J. Solid-State Circuits, vol. 45, pp. 2466-2475, Nov. 2010.
[54]C.-H. Wu, L.-R. Chang-Chien, Transient response enhancement on the output-capacitorless low-dropout regulator using the multipath nested miller compensation with a transient quiescent current booster, IEICE Transactions on Electronics, Vol. E94-C, No. 9, Sept. 2011.
[55]C.-H. Wu, L.-R. Chang-Chien, Design of the output-capacitorless low-dropout regulator for nano-second transient response accepted to appear in the IET journal on Power Electronics, 2012.
[56]P. Y. Or and K. N. Leung, An output-capacitorless low-dropout regulator with direct voltage-spike detection, IEEE J. Solid-State Circuits, vol. 45, pp. 458-466, Feb 2010.
[57]K. N. Leung and P. Y. K. Mok Analysis of multistage amplifier-frequency compensation, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 48, pp. 1041-1056, Spe. 2001.
[58]Y. H. Lin, K. L. Zheng, and K. H. Chen, Smooth pole tracking technique by power mosfet array in low-dropout regulators, IEEE Trans. Power Electron., vol. 23, pp. 2421-2427, Sep 2008.
[59]K. N. Leung and Y. S. Ng, A CMOS low-dropout regulator with a momentarily current-boosting voltage buffer, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, pp. 2312-2319, Sep. 2010.
[60]M. Ho and K. N. Leung, Dynamic bias-current boosting technique for ultralow-power low-dropout regulator in biomedical applications, IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 58, pp. 174-178, Mar. 2011.
[61]J. P. Guo and K. N. Leung, A 6-μW chip-area-efficient output-capacitorless LDO in 90-nm cmos technology, IEEE J. Solid-State Circuits, vol. 45, pp. 1896-1905, Sep. 2010.
[62]K. N. Leung, Y. Y. Mai, and P. K. T. Mok, A chip-area efficient voltage regulator for VLSI systems, IEEE Trans. on VLSI Systems, vol. 18, pp. 1757-1762, Dec. 2010.
[63]C. Zheng, and D. S. Ma, Design of monolithic cmos ldo regulator with coupling and adaptive transmission control for adaptive wireless powered bio-implants, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, pp. 2377-2386, Oct. 2011.
[64]G. Wang et al. Design and analysis of an adaptive transcutaneous power telemetry for biomedical implants, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, pp. 2109-2117, Oct. 2005.
[65]X. H. Fan, C. Mishra, and E. Sanchez-Sinencio, Single miller capacitor frequency compensation technique for low-power multistage amplifiers, IEEE J. Solid-State Circuits, vol. 40, pp. 584-592, Mar 2005.
[66]W. J. Huang, S. H. Lu, and S. I. Liu, CMOS low dropout linear regulator with single Miller capacitor, Electronics Letters, vol. 42, pp. 216-217, Feb 2006.
[67]W. Oh and B. Bakkaloglu, A CMOS low-dropout regulator with current-mode feedback buffer amplifier, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, pp. 922-926, Oct 2007.
[68]C. L. Shi, B. C. Walker, E. Zeisel, B. Hu, and G. H. McAllister, A highly integrated power management IC for advanced mobile applications, IEEE J. Solid-State Circuits, vol. 42, pp. 1723-1731, Aug 2007.
[69]W. Oh, B. Bakkaloglu, C. Wang, and S. K. Hoon, A CMOS low noise, chopper stabilized low-dropout regulator with current-mode feedback error amplifier, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, pp. 3006-3015, Nov 2008.
[70]M. Al-Shyoukh and H. Lee, A compact ramp-based soft-start circuit for voltage regulators, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, pp. 535-539, Jul 2009.
[71]C. Y. Hsieh, C. Y. Yang, and K. H. Chen, A low-dropout regulator with smooth peak current control topology for overcurrent protection, IEEE Trans. Power Electron., vol. 25, pp. 1386-1394, Jun. 2010.
[72]C. Zheng and D. S. Ma, Design of monolithic low dropout regulator for wireless powered brain cortical implants using a line ripple rejection technique, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, pp. 686-690, Sep. 2010.
[73]E. N. Y. Ho and P. K. T. Mok, Wide-loading-range fully integrated ldr with a power-supply ripple injection filter, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, pp. 356-360, Jun. 2012.
[74]J.-H. Wang, C.-H. Tsai, and S.-W. Lai, A low-dropout regulator with tail current control for dpwm clock correction, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, pp. 45-49, Jan. 2012.
[75]Y. I. Kim and S. S. Lee, Fast transient capacitor-less LDO regulator using low-power output voltage detector, Electronics Letters, vol. 48, pp. 175-177, Feb. 2012.
[76]M. Xin, L. Qiang, Z. Ze-kun, and Z. Bo, An ultrafast adaptively biased capacitorless ldo with dynamic charging control, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, pp. 40-44, Jan. 2012.
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