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研究生:楊昆霖
研究生(外文):Kun-LinYang
論文名稱:27-GHz CMOS 壓控振盪器之研製
論文名稱(外文):Implementation of a 27-GHz Voltage-Controlled Oscillator
指導教授:黃尊禧
指導教授(外文):Tzuen-Hsi Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:78
中文關鍵詞:低功率相位雜訊交叉耦合對壓控振盪器
外文關鍵詞:low powerphase noisecross-couple pairvoltage-controlled oscillator (VCO)
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在57~64-GHz毫米波頻段中,目前雖然尚未定義確切的系統規範,但是全世界各家大廠均已經在積極整合相關60-GHz毫米波積體電路。本篇論文主要考量低功率與低相位雜訊之特性,利用較為成熟0.18-um製程技術進行27-GHz壓控振盪器的設計。在未來搭配一個倍頻器的情況下可以提供一個54-GHz的訊號源。
透過國家晶片系統設計中心(CIC)的細心量測之下,測得振盪頻率為26.96~ 27.95-GHz,可調頻率範圍約1-GHz。在供應電壓為1.8V時,消耗功率為3.5mW;輸出功率為-7.88 dBm;在27-GHz量測到的相位雜訊為-99.39 dBc/Hz@1MHz offset和-120.94 dBc/Hz@10MHz offset;FOM指數為-182.56 dBc (@1MHz offset) ~ -184.11 dBc (@10MHz offset)之間;晶片面積大小為0.855*0.679 mm2。
本篇論文實現之晶片在相位雜訊與模擬之間有些許差異,電感以EM模擬後比較量測值相去不遠,預計未來對晶片內之走線、電感與電容進行EM模擬,以達到更精確之模擬結果,並將技術轉移到如90-nm CMOS先進製程之中,期望未來能達到低功率、高效能的整合目標。

Though the system standards for the applications in the V-band of 57 to 64 GHz are still not clear, the main leadership design companies have already put a great effort on the integration of 60-GHz mm-wave front-end circuits. In this thesis, a 27-GHz voltage-controlled oscillator (VCO) with low power and low phase-noise performances are designed in a mature 0.18-um CMOS process. This oscillator can provide a 54-GHz signal in the case with the help of a frequency doubler.
From the measurement results measured by CIC, the output frequency of the VCO ranging from 26.96 to 27.95 GHz (with a tuning range of about 1 GHz). The total power consumption is 3.5 mW from a 1.8V supply voltage. The output power is -7.88 dBm. The measured phase noise at 27 GHz is -99.39 dBc/Hz @ 1MHz offset and -120.94 dBc/Hz@10 MHz offset. The calculated figure-of-merits (FOM) are about in the range of -182.56 dBc (at 1 MHz offset) and -184.11 dBc (at 10 MHz offset). The chip size is about 0.855x0.679 mm2.
It is shown that there are some inconsistences between the measurement and simulation results of phase noise. After EM simulation of inductor, it found the result is similar to measurement. In the future, for the more precise simulation results, the layout of inter connection lines, inductors, and capacitances have to be taken into the design. Simultaneously, we would like to transfer this design from a 0.18um CMOS to a 90nm CMOS process, in order to achieve the lower power and higher performance.

摘要 I
Abstract II
誌謝 IV
目錄 V
表目錄 VII
圖目錄 VIII
第一章 緒論 1
1.1 研究背景與動機 1
1.2 論文組織架構 3
第二章 高頻LC諧振埠被動元件之特性 5
2.1 平面螺旋電感特性 5
2.1.1 平面方形螺旋電感之數學理論 6
2.1.2 平面螺旋電感之損耗來源 9
2.1.3 平面螺旋電感之等效模型與寄生效應 13
2.1.4 平面螺旋電感的品質因數 14
2.2 可變電容之特性 16
2.2.1 MOS可變電容基本原理及結構 16
第三章 振盪器原理與相位雜訊之介紹 21
3.1 振盪器基本原理 21
3.1.1 雙端回授系統分析 22
3.1.2 單端負阻式觀點分析 23
3.1.3 振盪器主要設計參數指標 29
3.2 相位雜訊 34
3.2.1 相位雜訊的定義 34
3.2.2 相位雜訊對通訊系統的影響 35
3.2.3 相位雜訊的來源 37
3.2.4 相位雜訊分析 38
3.2.5 相位雜訊頻譜 48
第四章27-GHz低功率高效能CMOS諧振壓控振盪器 51
4.1架構簡介 51
4.1.1 LC Tank的考量 52
4.1.2 主動埠架構的選擇 52
4.1.3 電流源設計的考量 55
4.1.4 緩衝器(buffer)的設計 57
4.2設計流程 58
4.3模擬與量測結果 59
4.3.1模擬結果 59
4.3.2 晶片量測結果 65
4.4 晶片佈局 70
4.5 結果與討論 71
第五章 結論與未來規劃 73
5.1 結論 73
5.2 未來規劃 73
參考文獻 75

[1]K. Sangsoo, K. Jeong-Geun, S. Taeksang, Y. Euisik, and H. Songcheol, 20 GHz integrated CMOS frequency sources with a quadrature VCO using transformers, in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Jun. 2004, pp. 269-272.
[2]P.-C. Huang, R.-C. Liu, H.-Y. Chang, C.-S. Lin, M.-F. Lei, H. Wang, C.-Y. Su, and C.-L. Chang, A 131 GHz push-push VCO in 90-nm CMOS technology, in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Jun. 2005, pp. 613-616.
[3]翁敏航, “射頻微機電元件技術與發展, 電子月刊, 2004 年12 月號, pp. 194-201.
[4]S. S. Mohan, M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, Simple accurate expressions for planar spiral inductances, IEEE Journal of Solid-State Circuits, vol. 34, no. 10, pp. 1419-1424, Oct. 1999.
[5]蔣宗佑,“低功率低相位雜訊CMOS 互補式LC諧振埠壓控震盪器之研究與分析, 國立雲林科技大學電子工程研究所碩士論文,民國九十四年七月
[6]Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, New York : Cambridge University Press, pp. 47-52, 1998.
[7]H. Ronkainen, H. Kattelus, E. Tarvainen, T. Ruhisaari, M. Andersson, and P. Kuivalainen, IC compatible planar inductors on silicon, IEE Proceedings of The Circuits, Devices and Systems, vol. 144, no. 1, Feb. 1997, pp. 29-35.
[8]H. J. De Los Santos, On the ultimate limits of IC inductors-an RF MEMS perspective, in Electronic Components and Technology Conference, 2002. Proceedings. 52nd, 2002, pp. 1027-1031.
[9]W. B. Kuhn and N. M. Ibrahim, Analysis of current crowding effects in multiturn spiral inductors, IEEE Transactions on Microwave Theory and Techniques, vol. 49, no. 1, pp. 31-38, Jan. 2001.
[10]B.-L. Ooi, D.-X. Xu, P.-S. Kooi, and F.-J. Lin, An improved prediction of series resistance in spiral inductor modeling with eddy-current effect, IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 9, pp. 2202-2206, Sept. 2002.
[11]K. Y. Tong and C. Tsui, A physical analytical model of multilayer on-chip inductors, IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 4, pp. 1143-1149, Apr. 2005.
[12]袁杰,高頻通信電路設計-被動網路,全華書局,民國83年
[13]Z. Jun, L. Chang, D. R. Trainor, J. Chen, J. E. Schutt-Aine, and P. L. Chapman, Development of three-dimensional inductors using plastic deformation magnetic assembly (PDMA), IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 4, pp. 1067-1075, Apr. 2003.
[14] 高曜煌,射頻鎖相迴路IC設計,滄海書局 2005
[15]劉深淵,楊清淵,鎖相迴路,滄海書局 2006.
[16]C. Samori, S. Levantino, and A. L. Lacaita, Integrated LC oscillators for frequency synthesis in wireless applications, IEEE Communications Magazine, vol. 40, no. 5, pp. 166-171, May. 2002.
[17]蔡穎傑,“最佳化電壓控制振盪器線路設計之研究,國立高雄應用科技大學電機工程研究所碩士論文,民國九十六年七月
[18]B. Razavi, RF Microelectronics, Prentice Hall, 1997.
[19]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 1996.
[20]通訊元件教學推廣中心,微波積體電路設計,教育部顧問室,民國九十六年三月
[21]柯俊瑋,“低相位雜訊及低功率CMOS壓控振盪器之設計, 國立中正大學電機工程研究所碩士論文,民國九十八年六月
[22]D. B. Leeson, A simple model of feedback oscillator noise spectrum, Proceedings of the IEEE, vol. 54, no. 2, pp. 329-330, Feb.1966.
[23]A. Hajimiri and T. H. Lee, A general theory of phase noise in electrical oscillators, IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[24]A. Hajimiri and T. H. Lee, Corrections to A General Theory of Phase Noise in Electrical Oscillators, IEEE Journal of Solid-State Circuits, vol. 33, no. 6, pp. 928-928, Jun. 1998.
[25]T. H. Lee and A. Hajimiri, Oscillator phase noise: a tutorial, IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.
[26]C. M. Hung, L. Shi, I. Laguado, and K. K. O, A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process, in Symposium on VLSI Circuits, 2000, pp. 100-101.
[27]J. P. Carr and B. M. Frank, A 38 GHz accumulation MOS differentially tuned VCO design in 0.18-um CMOS, in Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2006, pp.170-173
[28]J. O. Plouchart, K. Jonghae, N. Zamdmer, M. Sherony, T. Yue, Y. Meeyoung, M. Talbi, A. Ray, and L. Wagner, A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-um SOI CMOS technology, in Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC '03, 2003, pp. 357-360.
29] C.-H. Chiu, K.-H. Liang, H.-Y. Chang, and Y.-J. Chan, A low phase noise 26-GHz push-push VCO with a wide tuning range in 0.18-um CMOS technology, in Asia-Pacific Microwave Conference(APMC 2006), 2006, pp. 1128-1131.
[30]K. KaChun, J. R. Long, and J. J. Pekarik, A 23-to-29GHz Differentially Tuned Varactorless VCO in 0.13um CMOS, in IEEE International Solid-State Circuits Conference(ISSCC 2007), Feb. 2007, pp. 194-596.
[31]C. Changhua and K. K. O, A 90-GHz voltage-controlled oscillator with a 2.2-GHz tuning range in a 130-nm CMOS technology, in Symposium on VLSI Circuits, 2005, pp. 242-243.
[32]A. Hajimiri and T. H. Lee, Design issues in CMOS differential LC oscillators, IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May. 1999
[33]J. Yang, C. Y. Kim, D. W. Kim, and S. Hong, “Design of a 24-GHz CMOS VCO with an asymmetric-width transformer, IEEE Trans. Circuit Syst. II, vol. 57, no. 3, pp. 173–177, Mar. 2010.
[34]W. Liang, A. Ng, L. Leung, and H. C. Luong, A 24-GHz and 60-GHz dual-band standing-wave VCO in 0.13μm CMOS process, in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), May. 2010, pp. 145-148

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