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研究生:周佳緯
研究生(外文):Jia-WeiJhou
論文名稱:應用於單晶片矽除錯的電路核心事件觸發機制
論文名稱(外文):Inside-Core Event-Trigger Mechanism for SoC Silicon Debugging
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:46
中文關鍵詞:事件觸發矽除錯系統單晶片
外文關鍵詞:event triggersilicon debuggingsystem on a chip
相關次數:
  • 被引用被引用:0
  • 點閱點閱:135
  • 評分評分:
  • 下載下載:5
  • 收藏至我的研究室書目清單書目收藏:0
在對矽晶片除錯過程中,事件觸發技術被應用於監測一個電路或系統的狀態。當一個核心或系統的狀態滿足用戶所指定的事件或條件時,一些預先被設定好的除錯動作將會被觸發,例如將電路目前的狀態記錄下來或暫停正常運作的電路並取出電路內部資料且存放於記憶設備中。然而傳統的事件觸發技術通常只能觀察到一些數量有限並且需要預先定義的觸發信號,而這些限制使得事件觸發技術缺少重組觸發事件的能力。而在本論文中,我們提出了一個應用於單晶片矽除錯的電路核心事件觸發機制,它透過最常用的測試設計(掃描鏈)來監測一個待除錯電路內部的狀態。這個機制提供了許多強大的除錯能力,包括提取的掃描鏈上的任何內容、將多個觸發事件合併成一個單一的觸發條件、檢查觸發事件的排序順序、檢測指定的觸發事件發生的次數並可指定的一個搜索範圍來進行除錯。而我們使用硬體的方式來實現上述所有能力,因此可以有效率地對矽晶片進行除錯。我們將電路核心事件觸發機制實現在之前所開發的單晶片除錯平台中並提供了一個圖形視窗界面的硬體除錯工具用來支援事件驅動的除錯程序。實驗結果說明了我們所提出的電路核心事件觸發機制可以很方便的設置中斷點並檢查感興趣的暫存器,讓對硬體除錯就像對軟體開發進行除錯一樣,在觸發條件滿足時暫停正常運作的待除錯電路;當系統暫停時使用者可以檢查待除錯電路核心內部的所有狀態;而當檢查完成之後該系統可以恢復到其暫停之前狀態,然後使用者可以設置下一個觸發條件或進行單步執行的除錯。
Event-trigger techniques have been used to monitor the state of a core or system during post-silicon debugging. When a user-specified event or condition is satisfied, a pre-defined debugging operation such as snapshotting the current states of the core under debug and pausing the normal operation to enable the dumping of storage devices will be activated. However, the traditional event-trigger techniques usually can only observe a limited number of pre-determined trigger signals. They also lack the capability to reorganize the trigger events. In this work, we propose a flexible inside-core event-trigger mechanism that allows one to monitor all the internal registers of a core under debug through the most commonly employed test facility, i.e., scan chains. This mechanism provides several powerful debugging capabilities, including extracting the contents of any register on the scan chains, combining multiple trigger events into a single trigger condition, examining the sequencing order of events, detecting the number of occurrences of specified events, and performing debugging process in a specified search range. All the above capabilities are implemented in a hardware manner. Thus the silicon-debug process can be carried out efficiently. We have incorporated the inside-core event-trigger mechanism into an SOC debug platform, and provided a graphic user interface tool to support the event-driven debugging process. Experimental results show that the proposed inside-core event-trigger mechanism can facilitate breakpoint setting, examining the registers of interest and pausing the normal operation when the trigger condition is satisfied. The user can then examine the internal states of the core under debug when the system is paused. After the examination, the system can be recovered to its state right before it is paused. Thus the user can set another trigger condition or execute a single-step debug process, just like the debug process for software development.
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 PREVIOUS WORK 4
CHAPTER 2.1. HARDWARE-BASED EVENT-TRIGGER METHOD 4
CHAPTER 2.2. SOFTWARE-BASED EVENT-TRIGGER METHOD 8
CHAPTER 3 OVERVIEW OF THE INSIDE-CORE EVENT-TRIGGER MECHANISM 9
CHAPTER 3.1. OBJECTIVES OF THE INSIDE-CORE EVENT-TRIGGER MECHANISM 9
CHAPTER 3.2. THE INSIDE-CORE EVENT-TRIGGER MECHANISM 11
CHAPTER 3.3. DEBUG FLOW OF THE INSIDE-CORE EVENT-TRIGGER MECHANISM 13
CHAPTER 4 IMPLEMENTATION OF THE INSIDE-CORE EVENT-TRIGGER MECHANISM 15
CHAPTER 4.1. OVERALL ARCHITECTURE OF SOC DEBUG PLATFORM 15
CHAPTER 4.1.1. TAM Controller 17
CHAPTER 4.2. DESIGNS FOR INSIDE-CORE EVENT-TRIGGER MECHANISM 19
CHAPTER 4.2.1. Event Comparator 19
CHAPTER 4.2.2. The Clock Controller 28
CHAPTER 4.2.3. Hardware Debug Tool 29
CHAPTER 5 EXPERIMENTAL RESULTS 32
CHAPTER 5.1. EXPERIMENTAL ENVIRONMENT 32
CHAPTER 5.2. SIMULATION RESULTS 35
CHAPTER 5.3. EMULATION RESULT 37
CHAPTER 5.4. ANALYZING THE AREA OVERHEAD 38
CHAPTER 5.5. ANALYZING THE EVENT SEARCH TIME 40
CHAPTER 6 CONCLUSIONS 42
REFERENCES 43

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