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研究生:范銘倫
研究生(外文):Ming-LunFan
論文名稱:應用於低耗電系統之連續漸進式類比數位轉換器
論文名稱(外文):Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications
指導教授:楊慶隆楊慶隆引用關係
指導教授(外文):Chin-Lung Yang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:85
中文關鍵詞:類比數位轉換器連續漸進法低功率消耗
外文關鍵詞:analog-to-digital convertersuccessive-approximationlow-power
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本論文實現兩個架構應用於低功率消耗之系統的類比數位轉換器,其電路設計採用TSMC 0.18μm 1P6M製程實現之。第一個架構為單端輸入連續漸進式類比數位轉換器,採用PMOS與NMOS作為比較器的差動輸入級,以確保訊號的輸入範圍與供應電壓相同。此外,數位類比轉換器採用切換式電容電路的實現方式,以降低靜態消耗功率。此八位元轉換器所需供應電壓為1.8V,取樣頻率為每秒一百萬次與輸入頻率499.023千赫,其電路效能為訊號對雜訊與失真比為46.219 dB,積分非線性誤差與微分非線性誤差的範圍分別為-0.37 ~ 0.31 LSB與-0.37 ~ 0.51 LSB,整體功率消耗為273 μW,以及佈局面積(包含PAD)為780 μm × 780 μm。
第二個架構以全差動式連續漸進式類比數位轉換器實現。其中二級比較器不需參考偏壓源電路,以達到零靜態功率消耗。由差動電路架構的特性,降低雜訊影響進而增進電路的訊號雜訊比。十位元連續漸進式類比數位轉換器的效能於供應電壓1V、取樣頻率每秒一百萬次與輸入頻率149.4千赫,之訊號對雜訊與失真比為57.02 dB,積分非線性誤差與微分非線性誤差分別為-2.1 ~ 2.1 LSB與-1 ~2.2 LSB,整體功率消耗為22 μW,以及能量效率38 fJ/Conversion-step。
This thesis presents the two analog-to-digital converters for low-power system applications, and the circuit design is realized by using TSMC 0.18μm 1P6M process. The first architecture is a single-ended SAR-ADC, the PMOS and NMOS are adopted in the input differential stage of comparator to ensure the input signal range would be equal to the value of supply voltage. Besides, the realization of digital-to-analog converter is using switch-capacitor technique, which could reduce the static power dissipation. The result of 1.8V 1MS/s 8-bit SAR-ADC, shows the SNDR is 46.219 dB with 499.023 kHz input signal, INL and DNL is -0.37 ~ 0.31 LSB and -0.37 ~0.51 LSB, total power consumption is 273 μW, and the area of layout (including PAD) is 780 μm × 780 μm.
The second architecture is a fully-differential SAR-ADC. The modified two-stage comparator design except the bias circuit could reach the zero static power dissipation. Owing to the characteristic of differential circuit, it could reduce the noise effect to improve the SNR of circuits. The result of 1V 1MS/s 10-bit SAR-ADC, shows the SNDR is 57.02 dB by using the 149.4 kHz input signal, INL and DNL is -2.1 ~ 2.1 LSB and -1 ~2.2 LSB, total power consumption is 22 μW, and energy efficient is 38fJ/conversion-step.
摘要 I
Abstract II
致謝 IV
目錄 i
表目錄 iii
圖目錄 iv
第一章 緒論 1
1-1 研究動機 1
1-2 類比數位轉換器的實現方式 2
1-2.1 積分式類比數位轉換器 3
1-2.2 三角積分式類比數位轉換器 4
1-2.3 連續漸進式類比數位轉換器 5
1-2.4 循環式類比數位轉換器 6
1-2.5 管線式類比數位轉換器 7
1-2.6 快閃式類比數位轉換器 8
1-2.7 時間分離式類比數位轉換器 10
1-3 低耗能類比數位轉換器的選擇 11
1-4 差動輸入類比數位轉換器 12
1-5 各章節之概述 13
第二章 連續漸進式類比數位轉換器之原理與架構 15
2-1 連續漸進式演算法 15
2-2 連續漸進式類比數位轉換器之實現方式 16
2-2.1 單極輸入之電荷重新分配式類比數位轉換器 17
2-2.2 全差動式之連續漸進式類比數位轉換器 18
2-3 類比數位轉換器之重要參數介紹 19
2-3.1 解析度 19
2-3.2 量化誤差 19
2-3.3 量化誤差之頻譜密度 21
2-3.4 訊號對雜訊與失真比 22
2-3.5 動態範圍 23
2-3.6 非線性度 24
2-4 連續漸進式類比數位轉換器之功率消耗 26
第三章 單極輸入之連續漸進式類比數位轉換器 29
3-1 追蹤保持電路 30
3-1.1 追蹤保持電路的設計考量 30
3-1.2 寬擺幅輸入之追蹤保持電路 32
3-2 數位類比轉換器電路 34
3-2.1 電荷比例式數位類比轉換器電路之非線性度分析 34
3-3 連續漸進式控制電路 36
3-4 軌對軌比較器 38
3-4.1 偏壓電路 39
3-4.2 軌對軌前端放大電路 44
3-4.3 後端放大電路 46
3-4.4 軌對軌比較器模擬結果 47
3-5 單端輸入連續漸進式類比數位轉換器 48
3-6 相關文獻比較 50
3-7 佈局規劃 51
3-8 量測考量與結果 53
第四章 差動輸入之連續漸進式類比數位轉換器 57
4-1 取樣保持電路 58
4-1.1 導通電阻 58
4-1.2 通道電荷注入效應之解決方式 60
4-1.3 電荷幫浦式時脈驅動電路 62
4-1.4 靴帶式開關 63
4-2 連續漸進式控制電路 67
4-3 時脈控制式比較器 68
4-4 差動輸入之連續漸進式類比數位轉換器 73
4-5 文獻比較表 77
第五章 結論與未來展望 78
5-1 結論 78
5-2 未來展望 78
參考資料 81
附錄 A 數位類比轉換器電路 A
附錄 B 鎖相迴路之下線報告 G
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