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研究生:洪佳琪
研究生(外文):Chia-ChiHung
論文名稱:具有交錯存取架構的超低能耗靜態隨機存取記憶體
論文名稱(外文):Ultra-Low Energy Consumption SRAM with Wordline Interleaving Control
指導教授:邱瀝毅
指導教授(外文):Lih-Yih Chiou
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:87
中文關鍵詞:低能耗低電壓低功耗靜態隨機存取記憶體交錯控制字組線
外文關鍵詞:Low EnergyLow VoltageLow PowerSRAMWordline Interleaving
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隨著各式可攜式產品的不同功能需求增加,更多的功能被整合在一個面積受限的系統單晶片中,新一代的可攜式產品所消耗的能耗大幅增加且不容忽視,並導致供電電池的使用時間提前縮短,其中靜態隨機存取記憶體在系統晶片中佔據了極高的功耗比例,因此若是能儘量降低靜態隨機存取記憶體的能耗,渴望能使整體系統晶片受惠。
本篇論文提出一個採用字組線交錯控制機制、分割位元線和區域感測放大器等技術的改良架構,可降低存取功耗以及加速存取時間,進而達到較低能耗的目標,且僅使用單一電源以顧慮應用於可攜式產品時的系統層級成本考量。
上述所提出的設計以台積電九十奈米互補式金氧半導體製程技術,實現一個四千字元大小的近臨界電壓靜態隨機存取記憶體,從模擬結果顯示,這個具有改良架構的靜態隨機存取記憶體,可正確的操作在供應電壓為三百毫伏,能耗僅零點一三二微微焦耳,相較於傳統靜態隨機存取記憶體平均可節省55%的能耗及提升約1.91倍的操作速度。

With the increasing demands for versatile portable products, more and more functions are integrated into an area-constrained system. The energy consumed by the new-generation portable product increases dramatically and leads to short battery lifetime. Since the energy consumption of Static Random Access Memory (SRAM) occupies higher ratio than other components in systemona-chip(SoC), the overall system energy consumption can be lowered by reducing the energy consumption of SRAM.We propose a modified SRAM architecture that adopts wordline interleaving controller, hierarchical bit-lines and local sense amplifier methods to save energy consumption and to reduce access time. Besides, this work also maintains only one supply voltage as a power source to the SRAM for keeping the cost of portable products down under system level consideration. A 4Kb near-threshold SRAM macro with proposed techniques was implemented by using TSMC 90nm CMOS technology. According to the simulation results, the proposed SRAM can correctly operate at 0.3V supply voltage and only consume around 0.1323pJ. Compared to the traditional 6T SRAM, our proposed SRAM has an average 55% energy saving and around 1.91 times access speed improvement.
圖目錄 vii
表目錄 x
第 1 章 緒論 1
1.1 研究背景 1
1.2 研究動機 6
1.3 研究貢獻 7
1.4 論文架構 9
第 2 章 低能耗靜態隨機存取記憶體於低電壓操作的考量 11
2.1 傳統六電晶體記憶體的分析 11
2.2 低電壓下的穩定度問題 13
2.2.1 讀取錯誤與靜態雜訊邊界 13
2.2.2 寫入錯誤與寫入時間 16
2.2.3 存取錯誤與讀取電流和漏電流比例 17
2.3 低電壓下的存取時間問題 19
2.4 低電壓下的功率消耗問題 22
2.5 總結 23
第 3 章 相關研究 25
3.1 改良記憶體細胞元電路 25
3.1.1 以降低功耗為主的改良方式 [14-17] 25
3.1.2 以提高操作速度為主的改良方式 [18-21] 27
3.2 增加輔助電路的改良方式 [7, 22-25] 29
3.3 改良記憶體架構的方式 32
3.3.1 記憶體位元線架構的改良方式 [29-34] 32
3.3.2 記憶體字組線架構的改良方式 [35-39] 34
3.4 總結 37
第 4 章 提出的低能耗SRAM設計 39
4.1 WIC SRAM的整體架構概述 39
4.2 達到低功耗的字組線設計 42
4.2.1 列解碼器與字組線交錯控制器 42
4.2.2 字組線控制器與記憶體陣列 44
4.3 提升存取速度的位元線設計 46
4.3.1 分割位元線技術與區域輔助電路 47
4.3.2 能耗與面積的分析 50
4.4 讀取與寫入操作 52
4.5 與傳統SRAM的佈局面積比較 54
4.6 內建自我測試電路的設計 56
第 5 章 實驗模擬結果 59
5.1 操作電壓範圍模擬 59
5.1.1 模擬波形說明 59
5.1.2 操作電壓模擬與製程變異考量 61
5.1.3 低電壓的讀取動作與靜態雜訊邊界模擬 64
5.1.4 低電壓的寫入動作與寫入時間模擬 66
5.1.5 低電壓下存取電流對漏電流的模擬 68
5.2 功耗與效能模擬 69
5.3 能耗與製程變異模擬 72
5.3.1 不同操作電壓的能耗模擬 72
5.3.2 不同的製程變異下的能耗模擬 73
5.4 內建自我測試電路的模擬 75
5.5 與相關文獻之效能比較 77
5.6 佈局及晶片實現 80
第 6 章 結論與未來展望 81
6.1 結論 81
6.2 未來工作 82
參考文獻 83

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