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研究生:翁培恩
研究生(外文):Pei-EnWeng
論文名稱:針對電子系統層級虛擬平台考慮電壓和頻率調變之具有架構感知並以指令為基礎的功率模型
論文名稱(外文):Architecture-Aware Instruction-Based Power Model Considering Voltage and Frequency Scaling For ESL Virtual Platforms
指導教授:邱瀝毅
指導教授(外文):Lih-Yih Chiou
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:65
中文關鍵詞:功率模型電壓頻率調變
外文關鍵詞:Power modelVoltage and frequency scaling
相關次數:
  • 被引用被引用:0
  • 點閱點閱:157
  • 評分評分:
  • 下載下載:7
  • 收藏至我的研究室書目清單書目收藏:0
在現今的設計中,數位電路的功率消耗已經成為一個越來越重要的問題,硬件解決方案是動態調變電路的電壓和頻率,軟件解決方案則是藉由任務調度和線程遷移避免電路內功能模組同時產生功率消耗,因此我們需要在一個電子系統層級虛擬平台並集成功率模型以執行快速地軟硬體協同模擬,它可以幫助設計人員開發電源管理算法以便動態調整工作電壓和頻率。
在本篇中,我們針對匯流排、通用處理器和記憶體建立功率模型,實驗結果表示,高階處理器功率模型與PrimeTime PX兩者功率分析結果相比較,誤差可被限制在5%以內。
Power consumption of digital electronic has become one of the important issues in recent years. Voltage and frequency of a module can be configured dynamically to reduce power consumption of hardware. Each block can be avoided simultaneously activating to consume power by using task scheduling of the software. Therefore, an electronic-system level virtual platform integrated with power models to perform fast software and hardware co-simulation is needed. It can help designers developing power management algorithms to dynamically adjust the operating voltage and frequency of the system.
In this work, we have developed power models for a general-purpose processor, memories and a subsystem. Experimental results show that the high-level processor power model can be confined within 5% of errors of the power obtained by PrimeTime.
Chapter I Introductions 1
I.1 Background 1
I.2 Mechanisms of Power Optimization 2
I.3 Power Estimation with Platforms 4
I.4 Acknowledgements 5
I.5 Contribution 6
I.6 Thesis Organization 6
Chapter II Related Works 7
II.1 Abstraction Levels of Power Models 7
II.1.1 Inter-Instruction Effect 10
II.2 Platforms with Power Models 11
II.3 Considerations of Voltage and Frequency 17
II.4 Summary 20
Chapter III Modeling Methods 24
III.1 Target Platform 24
III.2 Early Analysis 26
III.3 General Power Modeling 27
III.3.1 Power Modeling for Logic Parts of the Core 28
III.3.2 Power Modeling for Memory Parts of the Core 32
III.3.3 Power Modeling for PMU 33
III.3.4 Power Modeling for Bus Subsystem 34
III.4 Power Modeling for Operating Points 36
III.5 Power Calculations 36
Chapter IV Experimental Results 39
IV.1 Modeling Flow 39
IV.2 Analytic Results 41
IV.3 Accuracy Validations 50
Chapter V Conclusions and Future Works 58
V.1 Conclusions 58
V.2 Future Works 58
References 60
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