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研究生:吳冠麟
研究生(外文):Kuan-LinWu
論文名稱:具有自適應性資料保持電壓調節電路之極低待機功率靜態隨機存取記憶體
論文名稱(外文):An Adaptive Data-Retention-Voltage Regulating Scheme for Ultra-Low Standby Power SRAMs
指導教授:邱瀝毅
指導教授(外文):Lih-Yih Chiou
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:67
中文關鍵詞:靜態隨機存取記憶體資料保持電壓待機功率
外文關鍵詞:SRAMData-retention-Voltage (DRV)Standby power
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  • 下載下載:7
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隨著先進製程的微縮,使得漏電功率成為靜態隨機存取記憶體最重要的挑戰之一。在傳統的設計中,積體電路設計者藉由將待機電源降低至資料保持電壓來大幅節省靜態隨機存取記憶體的待機功率。但是他們並沒有考量在輕載條件下之電壓轉換器的低轉換效率,這會損害從待機電源降低所獲得的好處。另一方面,資料保持電壓在受到製程、電壓及溫度漂移的影響也會增加設計的複雜度。在本篇論文當中,提出了使用自適應性資料保持電壓調節電路來降低靜態隨機存取記憶體的待機功率。此電路因為不使用在輕載條件下的電壓轉換器來當作待機電源,所以並沒有電壓轉換器額外的功率消耗。另外,此電路藉由所提出資料保持電壓監控器來追蹤靜態隨機存取記憶體的資料保持電壓並透過所提出的動態偏壓技術的幫助來補償資料保持電壓監控器的反應速度,使得自適應調節資料保持電壓電路可以在受到製程、電壓及溫度漂移的影響自我調節。此外,此電路可支援資料保持電壓位於次臨界電壓區域至臨界電壓區域的操作。在後佈局的模擬結果中指出,所提出的設計可以降低87.2%的靜態隨機存取記憶體的待機功率。
With the advancement of technology scaling, the leakage power issue becomes one of the most important challenges for SRAMs. Traditionally, IC designers lower the standby VDD to data-retention-voltage (DRV) to reduce SRAM standby power aggressively by voltage converters. However, they do not consider the low efficiency of voltage converters under light loads, which subsequently may degrade the benefit using VDD scaling. On the other hand, the impact of process, voltage and temperature (PVT) variations on DRV also increases the design complexity. In this thesis, we propose an adaptive data-retention-voltage regulating scheme (ADRVRS) to reduce SRAM standby power. This scheme has no extra power overhead of voltage converters because we do not use the voltage converters as standby VDD under light loads. Besides, our scheme can self-adapt DRV on PVT through the proposed DRV monitor tracking SRAM’s DRV and the proposed dynamic bias technique compensating the reaction speed of the DRV monitor. Moreover, the proposed scheme can support operation of DRV from above-threshold to sub-threshold regions. In the post-layout simulation results, we obtain 87.2% SRAM standby power reduction.
Abstract (Chinese) i
Abstract (English) ii
Acknowledgement iii
Contents iv
List of Tables vi
List of Figures vii
Chapter 1 Introduction 1
1.1 Background 1
1.1.1 Preliminary 1
1.1.2 Data retention voltage (DRV) 4
1.2 Motivation 6
1.3 Contributions 8
1.4 Thesis Organization 9
Chapter 2 Standby VDD Scaling Schemes for Ultra-Low Standby Power SRAMs 11
2.1 General Standby VDD scaling Schemes 11
2.1.1 Open-loop approach: the worst case design 12
2.1.2 Open-loop approach: calibration at test time 13
2.1.3 Closed-loop approach 15
2.2 Without Using Voltage Converters Schemes 17
2.2.1 Data-retention power gating technique 17
2.2.2 Stacked SRAM 18
2.2.3 Self-refreshing regulation 19
2.3 Summary 20
Chapter 3 Proposed Adaptive Data-Retention-Voltage Regulating Scheme (ADRVRS) Design 23
3.1 System Architecture Overview 23
3.2 Operation Flow of the ADRVRS 26
3.3 Proposed ADRVRS Circuit Design 34
3.3.1 Sub-header 34
3.3.2 DRV monitor 35
3.3.3 Data-loss detector 38
3.3.4 Regulating controller 39
3.3.5 Dynamic bias generator 42
Chapter 4 Test Chip Implementation 43
4.1 Chip Architecture 43
4.2 SRAM Design 45
4.3 BIST Design 46
Chapter 5 Simulation Results 49
5.1 Simulation Environment Setup 49
5.1.1 Proposed ADRVRS environment setup 49
5.1.2 Test chip environment setup 51
5.1.3 The pre-analysis of DRV 52
5.2 Simulation Results of the ADRVRS Design 53
5.3 Simulation Results of Test Chip Design 55
5.4 Comparison 59
Chapter 6 Conclusions and Future Work 61
6.1 Conclusions 61
6.2 Future Work 62
References 63
Autobiography 67

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