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研究生:翁明瀚
研究生(外文):Ming-HanWeng
論文名稱:混合式互聯應用於多核心平台之效能評估
論文名稱(外文):Evaluating the Performance of a Hybrid Interconnect in Many-Core Platform
指導教授:陳中和陳中和引用關係
指導教授(外文):C. H. Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電腦與通信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:77
中文關鍵詞:晶片網路快取一致性混合式互聯目錄式快取一致性協定
外文關鍵詞:Cache CoherencyDirectory-based Cache Coherence ProtocolHybrid InterconnectNetwork-on-Chip(NoC)
相關次數:
  • 被引用被引用:0
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  • 下載下載:8
  • 收藏至我的研究室書目清單書目收藏:0
傳統上多核心系統是以匯流排(bus)作為互聯(interconnect),它的傳遞延遲較低。但是它一次只能服務一個核心(core),隨著core的數量越來越多,它便開始成為效能上的瓶頸。因此,有人提出晶片網路(Netwok on Chip, NoC)作為多核心系統的interconnect。由於以NoC為interconnect的多核心系統廣播(broadcast)較為困難,無法以傳統bus上的偵聽式協定(snoop-based Protocol)去維持快取一致性(cache coherency)。因此,在NoC上多採用目錄式協定(directory-based protocol)去維持晶片上的cache coherency。
在本論文中,我們以SystemC語言實作NoC的時間近似模型(approximate-timed model),將其應用於多核心平台,並且在NoC上實作MESI directory-based cache coherence protocol,並且以此平台針對SPLASH-2驗證程式(benchmark)進行分析。此外,我們提出了一種混合式互聯(hybrid interconnect)以減少NoC上的traffic。我們以SPLASH-2對此hybrid interconnect進行效能評估,實驗結果顯示,相較於8核、16核,以及32核的純NoC-based interconnect,traffic分別可以減少53%,45%與39%。

Traditionally, a bus interconnect is used as the interconnect in a multi-core system due to its low transmission delay. However, it can only serve one master core at a time, and thus becomes a bottleneck when the number of cores increases in the system. Therefore, Network-on-Chip (NoC) is proposed as the interconnect of a many-core platform. In a NoC-based many-core system, broadcast is costly, so we can’t apply the snoop-based cache coherence protocol to maintain the cache coherency. For this reason, a directory-based cache coherence protocol is commonly used for on-chip data coherency.
In this thesis, we use SystemC to implement an approximate-timed model of NoC, and realize the MESI directory-based cache coherence protocol. In addition, we develop a hybrid interconnect by clustering a small number of cores using bus to reduce the traffic in the NoC. We evaluate it by executing the SPLASH-2 Benchmarks. According to the experimental results, the hybrid internconet can reduce the traffic in the NoC by 53%, 45%, and 39% respectively with 8, 16, and 32 cores compared to the baseline without clustering.

摘要 I
ABSTRACT II
誌謝 III
目錄 IV
表目錄 VII
圖目錄 VIII
第1章 序論 1
1.1 研究動機 1
1.2 研究貢獻 2
1.3 論文編排 2
第2章 晶片網路(NOC) 4
2.1 NOC概述 4
2.1.1 Interconnect簡介 4
2.1.2 NoC與Multiprocessor Network的關係 7
2.1.3 NoC與Multicomputer Network的比較 7
2.2 NOC的TOPOLOGY 8
2.2.1 Mesh 8
2.2.2 Torus 9
2.2.3 Fat Tree 9
2.2.4 Butterfly Fat Tree (BFT) 10
2.2.5 OCTAGON 10
2.2.6 各種Topology的效能與成本評估 11
2.3 PROTOCOL 12
2.3.1 Switching 12
2.3.2 Routing 14
第3章 快取(CACHE) 17
3.1 CACHE COHERENCE PROTOCOL 17
3.1.1 Write Protocol 17
3.1.2 coherence state紀錄方式 18
3.1.3 coherence state model 19
3.2 L3 CACHE ARCHITECTURE 22
3.2.1 Non-Uniform Cache Access(NUCA) 22
3.2.2 Shared Cache的排列 23
第4章 相關研究 25
4.1 MANY-TO-FEW傳輸特性 25
4.2 THE POWER OF PRIORITY 27
4.3 使用硬體進行COHERENCE的必要性 28
第5章 NOC的一致性與傳輸機制 29
5.1 MESI DIRECTORY-BASED CACHE COHERENCE PROTOCOL 29
5.1.1 L2 Cache的Coherence機制 30
5.1.2 L3 Cache的Coherence機制 31
5.2 THE CONNECTION PROTOCOL ON NOC 34
5.2.1 概述 34
5.2.2 Connection Types 34
5.2.3 拒絕與重傳 36
5.2.4 Suspend & Resume 36
5.2.5 Conflict 37
5.2.6 Interrupt 38
5.2.7 Flit格式 40
5.2.8 使用Connection Protocol的利弊分析 41
第6章 系統架構 43
6.2 MEMORY架構 43
6.3 NOC架構 44
6.3.1 NoC-based Interconnect 44
6.3.2 Hybrid Interconnect 45
6.4 元件介紹 46
6.4.1 Switch 46
6.4.2 Network Interface(NI) 48
6.4.3 L2 Cache Controller 53
6.4.4 L3 cache controller 56
第7章 實驗環境與數據分析 58
7.1 開發環境 58
7.2 實驗環境 59
7.2.1 驗證程式 59
7.2.2 參數設定 59
7.2.3 實驗方法 60
7.3 實驗結果 63
7.3.1 程式分析 63
7.3.2 Hybrid Interconnect之效能評估 69
7.3.3 Hybrid Interconnect的Cluster size對效能之影響 72
第8章 結論與未來展望 73
8.1 結論 73
8.2 未來展望 73
參考文獻 75

[1]Partha Pratim Pande, Cristian Grecu, and Michael Jones, “Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures, IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025-1040, Aug. 2005, doi:10.1109/TC.2005.134.
[2]Tobias Bjerregaard and Shankar Mahadevan, “A Survey of Research and Practices of Network-on-Chip, ACM Computing Surveys, Vol. 38, March 2006, Article 1.
[3]Erno Salminen et al., “Benchmarking mesh and hierarchical bus networks in system-on-chip context, Journal of Systems Architecture, pp. 477-488, August 2007.
[4]Mohammad Al-Fares, Alexander Loukissas, and Amin Vahdat A Scalable, Commodity Data Center Network Architecture, Proceedings of the ACM SIGCOMM 2008 conference on Data communication, August 17-22, 2008, Seattle, WA, USA.
[5]Cyriel Minkenberg and Mitch Gusat, IBM Research GmbH, Zurich,Bidirectional Fat Tree Construction and Routing for IEEE 802.1au.
[6]F. Karim, Anh Nguyen, and Sujit Dey, “An Interconnect Architecture for Networking Systems on Chips, IEEE Micro, vol. 22, no. 5, pp. 36-45, Sept./Oct. 2002.
[7]John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach,4th edition, 2006.
[8]Dennis Abts et al., “Achieving Predictable Performance through Better Memory Controller Placement in Many-Core CMPs,ISCA, 2009.
[9]Ali Bakhoda, John Kim, and Tor M. Aamodt,Throughput-Effective On-Chip Networks for Manycore Accelerators, IEEE Micro, pp. 421-432, 2010.
[10]Stefanos Kaxiras and Georgios Keramidas,SARC Coherence:Scaling Directory Cache Coherence in Performance and Power, IEEE MICRO, 2010.
[11]Jacob Leverich et al.,Comparing Memory Systems for Chip Multiprocessors, ISCA,2007.
[12]SystemC 2.0 User's Guide.
[13]S.-Y. Lee, “An Instruction Set Simulator with GDB Support and its Full System Simulation Virtual Platform, 2010 master thesis of National Cheng Kung University, Tainan, Tuaiwan, Jl. 2010.
[14]Evgeny Bolotin et al., The Power of Priority: NoC based Distributed Cache Coherency, International Symposium on Networks-on-Chip,2007.
[15]Seth H. Pugsley, et al., SWEL: Hardware Cache Coherence Protocols to Map Shared Data onto Shared Caches, PACT'10, September 11.15, 2010, Vienna, Austria.
[16]C.-T. Liu, “CASL Hypervisor and its Full System Virtualization Platform, 2012 master thesis of National Cheng Kung University, Tainan, Tuaiwan, Jl. 2012.

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