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研究生:蔡宗閔
研究生(外文):Tzung-Min Tsai
論文名稱:60GHz升頻混波器之設計與實現
論文名稱(外文):Design and Implementation of the 60GHz Up-Conversion Mixer
指導教授:林佑昇林佑昇引用關係
指導教授(外文):Yo-Sheng Lin
口試委員:孫台平梁效彬
口試委員(外文):Tai-Ping SunHsiao-Bin Liang
口試日期:2012-07-23
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:99
中文關鍵詞:60GHz升頻混波器Marchand巴倫負電阻補償技術轉換增益
外文關鍵詞:60GHzup-conversion mixerMarchand balunnegative-resistance compensation techniqueconversion gain
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本論文主要以台積電90奈米1P9M射頻CMOS製程來實現三個60GHz升頻混波器。研究主題分成了以下三個部份:
第一部份為60GHz升頻混波器使用雙平衡式混波器為主體架構,並且以Marchand巴倫(Balun)來達到LO輸入端的單端轉雙端與RF輸出端的雙端轉單端之功用,另外使用PMOS負電阻補償技術來提升轉換增益。使用台積電90奈米1P9M射頻CMOS製程來實現。
第二部份為57GHz~64GHz升頻混波器除了沿用第一部份所使用的電路架構,另外又採用了NMOS負電阻補償技術來配合PMOS負電阻補償技術,使其能夠提升轉換增益之外,亦能降低功率損耗。以台積電90奈米1P9M射頻CMOS製程來實現。
第三部份為57GHz~64GHz升頻混波器,目的是改善第一部份的轉換增益與其3dB頻寬,並且在轉導級增加一對NMOS對來改善與彌補因為提升增益而損失的IF頻寬。使用台積電90奈米1P9M射頻CMOS製程來實現。

This thesis mainly utilizes TSMC 90nm 1P9M RF CMOS process technology to implement three 60GHz up-conversion mixers. The thesis is composed of three sections:
In the first section, a 60GHz up-conversion mixer makes a double-balanced mixer as the main structure. With the Marchand balun, it can transfer a single-ended port to double-ended ports at the input of the LO port, and it also can convert double-ended ports to single-ended port at the output of the RF port. In addition, the dynamic current technique is used to increase the conversion gain. To implement the structure with the TSMC 90nm 1P9M RF CMOS process technology.
The second section is about a 57GHz ~ 64GHz up-conversion mixer, which is used with the structure of the first section. Besides, using the NMOS negative-resistance compensation technique to act in concert with the dynamic current technique to increase the conversion gain and decrease the power consumption. Applying the TSMC 90nm 1P9M RF CMOS process technology to implement the structure is the best choice.
The third section is about a 57GHz ~ 64GHz up-conversion mixer, and the purpose is to improve the conversion gain and the 3dB bandwidth of the first section. And to apply with another NMOS pair in the transconductance-stage to improve and recuperate the IF bandwidth when the conversion gain increases. To implement the structure with the TSMC 90nm 1P9M RF CMOS process technology.

Content

Chapter 1 Introduction

1.1 Motivation……………………………………………………………………………...1
1.2 Thesis Organization…………………………………………………………………...5

Chapter 2 Introduction for Basic Mixers

2.1 Introduction……………………………………………………………………………7
2.2 Parameters [1]…………………………………………………………………………7
2.2.1 Conversion Gain…………………………………………………………………7
2.2.2 Linearity: 1dB Gain Compression Point and Third-Order Intercept Point (P1dB & IP3)……………………………………………………………………...8
2.2.3 Isolation…………………………………………………………………………12
2.2.4 Return Loss……………………………………………………………………..12
2.2.5 Power Consumption……………………………………………………………13
2.3 Structure for the Mixer [3]…………………………………………………………14
2.3.1 Basic Mixer……………………………………………………………………..14
2.3.2 Single-Balanced Mixer [4]……………………………………………………16
2.3.3 Double-Balanced Mixer [4]……………………………………………………19
2.3.3.1 IF Input Amplify Stage………………………………………………..21
2.3.3.2 LO Modulation-Switching Stage……………………………………...21
2.3.3.3 RF Output Stage……………………………………………………….21
2.4 Consideration of the Layout…………………………………………………………22

Chapter 3 A 60GHz Up-Conversion Mixer with the PMOS
Negative-Resistance Compensation Technique Using
90nm Process

3.1 Structure of the Circuit………………………………………………………………25
3.1.1 Double-Balanced Mixer………………………………………………………..27
3.1.2 Marchand Balun [5]……………………………………………………………27
3.1.3 PMOS Negative-Resistance Compensation Technique [6]…………………31
3.2 Device-Parameter of the Proposed Circuit…………………………………………35
3.3 Simulated Results…………………………………………………………………….36
3.4 Measured Results…………………………………………………………………….42
3.5 Discussion……………………………………………………………………………..49
Appendix………………………………………………………………………………….51

Chapter 4 A 60GHz Up-Conversion Mixer with the NMOS
Negative-Resistance Compensation Technique Using
90nm Process

4.1 Structure of the Circuit………………………………………………………………55
4.1.1 NMOS Negative-Resistance Compensation Technique [7]…………………57
4.2 Device-Parameter of the Proposed Circuit…………………………………………60
4.3 Simulated Results…………………………………………………………………….61
4.4 Measured Results…………………………………………………………………….68
4.5 Discussion……………………………………………………………………………..75
Appendix………………………………………………………………………………….77

Chapter 5 A 60GHz Up-Conversion Mixer Using 90nm Process

5.1 Structure of the Circuit………………………………………………………………81
5.2 Device-Parameter of the Proposed Circuit…………………………………………83
5.3 Simulated Results…………………………………………………………………….84
5.4 Discussion……………………………………………………………………………..92

Chapter 6 Conclusion………………………........................................................95

Reference……………………………………………………………………………...97

Vita………………………………………………………………...99

List of Figures

Chapter 1 Introduction

Figure 1-1 Relation of the frequencies and the attenuations…………………………....3
Figure 1-2 Beam steering………………………………………………………………….4

Chapter 2 Introduction for Basic Mixers

Figure 2-1 1dB gain compression point…………………………………………………..9
Figure 2-2 Third-order intercept point………………………………………………….11
Figure 2-3 (a) Simple switch used as mixer, (b) implementation of switch with an NMOS device………………………………………………………………14
Figure 2-4 Basic structure of the active mixer………………………………………….15
Figure 2-5 Frequency translation………………………………………………………..16
Figure 2-6 Schematic of the single-balanced mixer…………………………………….18
Figure 2-7 (a) Double-balanced mixer…………………………………………………..19
Figure 2-7 (b) eliminating the LO to RF feedthrough…………………………………20
Figure 2-8 MSL with its electric field line distribution……………………………...…22
Figure 2-9 CPW with its electric field line distribution………………………………..23
Figure 2-10 Bend of the transmission line………………………………………………23




Chapter 3 A 60GHz Up-Conversion Mixer with the PMOS
Negative-Resistance Compensation Technique Using
90nm Process

Figure 3-1 Architecture of the mixer……………………………………………………26
Figure 3-2 Structure of the proposed circuit……………………………………………26
Figure 3-3 Marchand balun with four MSL……………………………………………28
Figure 3-4 Structure of the Marchand balun…………………………………………...28
Figure 3-5 S-Parameter of the proposed balun…………………………………………29
Figure 3-6 Phase difference of the proposed balun…………………………………….30
Figure 3-7 Insertion loss of the proposed balun………………………………………..30
Figure 3-8 Schematic of the current injection technique………………………………31
Figure 3-9 Schematic of the proposed PMOS negative-resistance compensation technique………………………………………………………………32
Figure 3-10 PMOS negative-resistance compensation technique……………………..33
Figure 3-11 Equivalent circuit of the PMOS negative-resistance compensation
technique…………………………………………………………………33
Figure 3-12 Simulation of the return loss, (a) IF port…………………………………36
Figure 3-12 Simulation of the return loss, (b) LO port, (c) RF port………………….37
Figure 3-13 Simulation of the conversion gain……………………….………………38
Figure 3-14 Simulation of the IF bandwidth …………………………………………39
Figure 3-15 Simulation of the LO to RF isolation ……………………………………40
Figure 3-16 Simulation of the 1dB gain compression point …………………………40
Figure 3-17 Simulation of the input third-order intercept point……………………41
Figure 3-18 Layout of the circuit………………………………………………………..42
Figure 3-19 Measurement of the return loss, (a) IF port, (b) LO port……….………43
Figure 3-19 Measurement of the return loss, (c) RF port……………………………..44
Figure 3-20 Measurement of the conversion gain ……………………………………..45
Figure 3-21 Measurement of the IF bandwidth………………………………………...45
Figure 3-22 Measurement of the LO to RF isolation…………………………………..46
Figure 3-23 Measurement of the 1dB gain compression point………………………...47
Figure 3-24 Measurement of the input third-order intercept point…………………..47
Figure 3-25 Die photo of this work……………………………………………………...48
Appendix 1. Measurement Method of the S-Parameter……………………………….51
Appendix 2. Measurement Method of the Conversion Gain and the IF Bandwidth...51
Appendix 3. Measurement Method of the LO to RF Isolation………………………...52
Appendix 4. Measurement Method of the 1dB Gain Compression Point…………….52
Appendix 5. Measurement Method of the Input Third-Order Intercept Point………53

Chapter 4 A 60GHz Up-Conversion Mixer with the NMOS
Negative-Resistance Compensation Technique Using
90nmProcess

Figure 4-1 Architecture of the mixer……………………………………………………56
Figure 4-2 Structure of the proposed circuit……………………………………………56
Figure 4-3 Schematic of the proposed NMOS negative-resistance compensation
technique…………………………………………………………………….57
Figure 4-4 NMOS negative-resistance compensation technique………………………58
Figure 4-5 Equivalent circuit of the NMOS negative-resistance compensation
technique…………………………………………………………………58
Figure 4-6 Simulation of the return loss, (a) IF port…………………………………..61
Figure 4-6 Simulation of the return loss, (b) LO port, (c) RF port…………………...62
Figure 4-7 Simulation of the conversion gain…………………………………………..63
Figure 4-8 Simulation of the IF bandwidth……………………………………………..64
Figure 4-9 (a) Simulation of the LO to RF isolation versus LO power, (b) Simulation of the LO to RF isolation versus frequency………………………………65
Figure 4-10 Simulation of the 1dB gain compression point……………………………66
Figure 4-11 Simulation of the input third-order intercept point………………………66
Figure 4-12 Layout of the circuit………………………………………………………..67
Figure 4-13 Measurement of the return loss, (a) IF port……………………………...68
Figure 4-13 Measurement of the return loss, (b) LO port, (c) RF port………………69
Figure 4-14 Measurement of the conversion gain……………………………………...70
Figure 4-15 Measurement of the IF bandwidth………………………………………...71
Figure 4-16 (a) Measurement of the LO to RF isolation versus LO power, (b)
Measurement of the LO to RF isolation versus frequency……………72
Figure 4-17 Measurement of the 1dB gain compression point………………………...73
Figure 4-18 Measurement of the input third-order intercept point…………………..73
Figure 4-19 Die photo of this work……………………………………………………...74
Appendix 1. Measurement Method of the S-Parameter……………………………….77
Appendix 2. Measurement Method of the Conversion Gain and the IF Bandwidth...77
Appendix 3. Measurement Method of the LO to RF Isolation………………………...78
Appendix 4. Measurement Method of the 1dB Gain Compression Point…………….78
Appendix 5. Measurement Method of the Input Third-Order Intercept Point………79

Chapter 5 A 60GHz Up-Conversion Mixer Using 90nm Process

Figure 5-1 Architecture of the mixer……………………………………………………82
Figure 5-2 Structure of the proposed circuit……………………………………………82
Figure 5-3 Simulation of the return loss, (a) IF port, (b) LO port………………...85
Figure 5-3 Simulation of the return loss, (c) RF port………………………………86
Figure 5-4 Simulation of the conversion gain…………………………………………..87
Figure 5-5 Simulation of the IF bandwidth……………………………………………..88
Figure 5-6 (a) Simulation of the LO to RF isolation versus LO power……………….88
Figure 5-6 (b) Simulation of the LO to RF isolation versus frequency……………….89
Figure 5-7 Simulation of the 1dB gain compression point……………………………..90
Figure 5-8 Simulation of the input third-order intercept point……………………….90
Figure 5-9 Layout of the circuit…………………………………………………………91

List of Tables

Chapter 1 Introduction

Table 1-1 Indicators for all the alliances…………………………………………………3

Chapter 3 A 60GHz Up-Conversion Mixer with the PMOS
Negative-Resistance Compensation Technique Using
90nm Process

Table 3-1 Device-parameter of this work……………………………………………….35
Table 3-2 Comparison table of the simulation and the measurement………………...49
Table 3-3 Comparing with the references………………………………………………50

Chapter 4 A 60GHz Up-Conversion Mixer with the NMOS
Negative-Resistance Compensation Technique Using
90nm Process

Table 4-1 Device-parameter of this work……………………………………………….60
Table 4-2 Comparison table of the simulation and the measurement………………...75
Table 4-3 Comparing with the references………………………………………………76


Chapter 5 A 60GHz Up-Conversion Mixer Using 90nm Process

Table 5-1 Device-parameter of this work……………………………………………….83
Table 5-2 Comparing with the references………………………………………………93

Chapter 6 Conclusion

Table 6-1 Comparison of all works…………………………………………………......96








Reference
[1] Pao-Yung Chih, Chih-Ping Yu, Ping-Hsueh Shih, “Analysis and Design of CMOS
RF Integrated Circuits,” Jan. 2006, pp. 214-221.
[2] http://ardentech.com/webhelp/Scw32Component_Properties_Parameters_.htm
[3] Behzad Razavi, “RF Microelectronics.” USA: Prentice Hall, 1997, pp. 166-200.
[4] Kun-Yu Chen, “The design of 5.2GHz low voltage and low power consumption
mixer with current reuse.” Chung Hsing University, Taiwan, 2007.
[5] Chia-Hsieh Liu, “Research on CMOS RFICs and Passive Key Components Design
for 60-GHz Millimeter-Wave RF Front—End.” Cheng Kung University, Taiwan, Jul, 2007, pp. 21-24.
[6] Zhong-Cheng Su, Zhi-Ming Lin, “A 18.9dB Conversion Gain Folded Mixer for
WiMAX System,” IEEE, 2008, pp.292-295.
[7] Chang-Hsi Wu, Wen-Hui Huang, “A High-Linearity Up-Conversion Mixer
Utilizing Negative Resistor,” ISSSSE, 2010, pp.1-4.
[8] Michael Kraemer, Daniela Dragomirescu, and Robert Plana,” A Dual-gate 60GHz
Direct Up- conversion Mixer with Active IF Balun in 65nm CMOS,” Universit´e de
Toulouse; UPS, INSA, INP, ISAE; LAAS; F-31077 Toulouse, France,2010, pp.1-4.
[9] Mohamed Elkhouly, Srdjan Glisic, Christoph Scheytt,” A 60 GHz Wideband High
Output P1dB Up-conversion Image Rejection Mixer in 0.25 μm SiGe Technology”,
IHP-microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany,
2010, pp. 49-52.
[10] Minsu Ko, Holger Rücker, and Woo-Young Choi,” A 53–64-GHz SiGe
Up-Conversion Mixer with 4-GHz IF Bandwidth,” Yonsei University, Seoul
120-749, Korea;IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany,
2010, pp. 73-76.
[11] Min-Chiao Chen, Huan-Sheng Chen, Tzu-Chao Yan, and Chien-Nan Kuo,” A CMOS Up-Conversion Mixer with
Wide IF Bandwidth for 60-GHz Applications,” National Chiao Tung University, Hsinchu, Taiwan,
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[12] Pei-Si Wu, Chi-Hsueh Wang, Chin-Shen Lin, Kun-You Lin, Huei Wang,” A Compact
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[13] F. Zhang, E. Skafidas, W. Shieh, B. Yang, B. N. Wicks and Z. Liu,” A 60-GHz
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University of Melbourne, VIC 3010, Australia, 2008, pp. 1-4.



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