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研究生:劉昱昌
研究生(外文):Liu, Yuchang
論文名稱:以0.18微米CMOS製程設計和實現之10位元250MHz電流導向數位類比轉換器
論文名稱(外文):Design and Implementation of a 10-bit 250-MS/s Current Steering Digital-to-Analog Converter in 0.18μm CMOS Process
指導教授:林佑昇林佑昇引用關係
指導教授(外文):Lin, Yosheng
口試委員:孫台平梁效彬
口試委員(外文):Sun, TaipingLiang, Hsiaobin
口試日期:2012-07-23
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:61
中文關鍵詞:電流導向式數位類比轉換器溫度計碼二進位權重碼
外文關鍵詞:current steering DACthermometer decoderweighted binary code
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本論文模擬和佈局實現一個十位元取樣頻率250MHz的電流導向式數位類比轉換器,並利用台積電提供的TSMC 0.18µm 1P6M實現一個電路,電路架構分數位和類比兩個部分,為了減少突波效應、整體非線性誤差、差異非線性誤差,且為了保持轉移曲線的單調性,所以使用分段式架構,輸入為十位元的數位訊號,其最高六位元使用溫度計碼,最低四位元為二進位權重碼,而架構主要分四個部分(一)、數位電路(二)、時脈電路、緩衝器(三)、deglitch閂鎖電路 (四)、電流源單元。且電流導向數位類比轉換器的輸出電流不需要一輸出緩衝器就可以直接驅動負載電阻,因此在速度上相較於其他架構有優勢。最後在量測時先以類似此架構量測TSMC 0.35µm DAC chip以其量測方式及其結果,做為本論文的量測為參考。
The simulation and layout of the thesis is to achieve a 250MHz 10bits current steering DAC, and is expected to complete tape out by 0.18um 1p6m process provided by Taiwan Semiconductor Manufacturing Company provided . The circuit layout design has two parts - digital and analog. To reduce the glitch and differential nonlinearity (DNL), integral nonlinearity (INL) and to maintain the transfer curve monotonic the circuit is designed to be segmented structure, in which the highest 6bits MSB is the thermometer decoder and the lowest 4bits LSB is weighted binary code. The circuit is composed of 4 main parts: (1) digital circuit (2) clock drive, buffer (3) Deglitch Latch (4) current units. And current steering DAC output current do not need to output buffer can Directly drive the load resistance, so better than other architecture has speed advantages. Finally, first measurements to similar measurements of this structure TSMC 0.35μm the DAC chip for its measurement method and its results as a measurement of the paper as a reference.
Contents

Chinese Abstract I
English Abstract II
Contents III
List of Figures V
List of Tables VIII


Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2

Chapter 2 Fundamental of
Digital-to-Analog converter 3
2.1 Motivation 3
2.2 Fundamental of Digital to Analog converter 4
2.2.1 Introduction 4
2.2.2 Specifications of Digital-to-Analog Converter 6
2.2.3 Review Digital-to-Analog Converter Architecture 14
2.3 Summary 22

Chapter 3 Implementation of Current-steering
D/A Converter 23
3.1 Design Consideration for current-steering DAC 23
3.2 Implementation of Current-steering D/A converter 27
3.2.1 Introduction 27
3.2.2 The architecture of proposed 30
3.2.3 Digital Circuitry 32
3.2.4 Analog Circuitry 39
3.3 Simulation Results and Discussions 44
3.4 Summary 50

Chapter 4 Measurement Results 51
4.1 Measurement Board Planning 51
4.2 Measurement Setup 52
4.3 Measurement Results 53
4.3.1Measurement results TSMC 0.35µm DAC chip 53
4.3.2Measurement results TSMC 0.18µm DAC chip 56

Chapter 5 Conclusions 58
Conclusions 58
References 59
Vita 61

References
[1] Steven Shepard,〝RFID Radio Frequency Identification〞New York,McGraw-Hill , 2005
[2] 林佑昇,邱弘緯,梁效彬,〝RFID 晶片設計〞中華民國100年1月初版發行
[3]Rudy van de Plassche, Broadcom Netherlands BV, The Netherlands and Broadcom, Irvine, CA, U.S.A.〝CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters 2nd Edition〞Baker & Taylor Books, 2003-05-31
[4]Allen、Holberg 〝CMOS Analog circuit Design〞oxford university press all rights reserved 2002
[5]R.Jacob Baker 〝CMOS Mixed-Signal Circuit Design second edition〞WILEY 2009
[6]R.Jacob Baker 〝CMOS circuit design, layout, and simulation〞WILEY 2007
[7] David Johns, Ken Martin〝Analog Integrated Circuit Design〞John Wiley & Sons, 1996-11-15
[8]徐偉宏,"具十二位元解析度每秒250萬次取樣頻率之數位類比轉換器" 國立成功大學電機工程學系碩士論文中華民國 九十三 年 七 月
[9]潘春明,"可應用於無線區域網路之十位元100MHz電流導向數位類比轉換器" 國立成功大學積體電路製程即封裝測試產業研發碩士專班論文中華民國 九十七 年 一 月
[10]陳仁禮,"十位元1GHz電流導向式數位類比轉換器" 國立成功大學電機工程學系碩士論文中華民國 九十四 年 七 月
[11]張峻旗,"具低成本自我校正之十四位元每秒一億次取樣之數位類比轉換器"國立成功大學電機工程學系碩士論文中華民國 九十六 年 七 月
[12] Jurgen Deveugele, Member, IEEE, and Michiel S. J. Steyaert, Fellow, IEEE〝A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC〞IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
[13] Jaejin Jung, Kwang-Hyun Baek, Shin-Il Lim, Suki Kim, Sung-Mo Kang School of Electronic Engineering, Korea University, Seoul, Korea School of Electrical and Electronics Engineering,Chung-Ang University, Seoul, Korea Dept. of Computer Engineering, Seokyeong University, Seoul, Korea School of Engineering,University of California, Merced,〝Design of a 6 bit 1.25 GS/s DAC for WPAN〞
[14] Jae-Jin Jung, Bong-hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim “A 6-bit 2.704Gsps DAC for DS-CDMA UWB”
[15] Ren-Li Chen and Soon-Jyh Chang Department of Electrical Engineering National Cheng Kung University〝A 5-bit 1.35-GSPS DAC for UWB Transceivers〞ICUWB 2009 (September 9-11, 2009)
[16] *Jae-Jin Jung, **Bong-hyuck Park, **Sang-Seong Choi, ***Shin-Il Lim, *Suki Kim “A 6-bit 2.704Gsps DAC for DS-CDMA UWB”
[17] Kevin 0' Sullivan, Chris Gorman, Michael Hennessy, Vincent Callagha” A 12b 320MSampleh Current-Steering CMOS D/A Converter in 0.44mm2”
[18] Pu Luo*, Weidong Yang, Dongbing Fu, and Jinshan Yu”A transistor matching technology improving effectively DC resolution of current-steering DAC”
[19] Ji Hyun Kim and Kwang Sub Yoon〝An 8-bit CMOS 3.3-V–65-MHz Digital-to-Analog Converter with a Symmetric Two-Stage Current Cell Matrix Architecture〞IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II—ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 12, DECEMBER 1998
[20] Behzad Razavi, "Design of Analog CMOS Integrated Circuits," Xi’an Jiaotong
University Press, China, Feb. 2003.

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