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研究生:陳享貴
研究生(外文):Chen, Siangguei
論文名稱:基於平行處理架構之模糊類神經網路晶片設計及其應用於圖形識別
論文名稱(外文):Parallel-Architecture-Based Fuzzy-Neural-Network Chip Design For Pattern Recognition
指導教授:吳俊德吳俊德引用關係
指導教授(外文):Wu, Ginder
口試委員:莊家峰洪志偉
口試委員(外文):Juang, ChiafengHung, Jeihweih
口試日期:2012-07-10
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:47
中文關鍵詞:模糊網路類神經網路平行運算架構
外文關鍵詞:fuzzy networkneural networkparallel computing architecturecell-based design flow
相關次數:
  • 被引用被引用:1
  • 點閱點閱:308
  • 評分評分:
  • 下載下載:60
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文提出一個平行運算架構模糊類神經網路晶片設計。模糊類神經網路晶片可以進行智慧學習功能而且應用於影像處理、語音訊號辨識和必需進行學習功能的系統之使用。這個模糊類神經網路架構是藉由接受外部指令而重構的。為了增強晶片的效能,我們提出了一個平行運算架構。這個運算架構可以平行處理不同的模糊化運算。最後,本晶片使用 TSMC 90nm 標準單元(standard cell)合成出晶片電路,並使用Cell-based設計流程進行晶片的設計以及驗證。晶片的規格如下,面積約為2.019x2.019 ,工作頻率為100MHz,消耗功率約為27.0911mW,gate count約為452845。
This research proposes a parallel computing architecture chip design of Fuzzy Neural Network. Fuzzy neural network chip can do intelligent learning function and applied to image processing, speech signal recognition and system that needs learning ability. The fuzzy neural network architecture is reconfigurable by receiving the instruction. In order to increase chip efficiency, we propose a parallel computing architecture. The computing architecture can parallely compute different fuzzifier processing. Finally, this FNN chip used synthesized by TSMC 90 nm standard cells library and using cell-based design flow for this chip design and verification. The specification of this chip, the chip area is about 2.019x2.019 and the maximum frequency is 100 MHz, power consumption is about 27.0911 mW, gate count is about 452845.
Acknowledgement.....I
Chinese abstract.....II
English abstract.....III
Contents.....IV
List of figures.....VI
List of tables.....VIII

1. Introduction.....1
1.1 Motivation.....1
1.2 Preview of fuzzy neural network.....2
1.3 Hardware implementation.....3
1.4 Organization of this Research.....4

2. Fuzzy neural network structure and learning algorithm.....5
2.1 TSK-type fuzzy set.....5
2.2 Structure of the fuzzy neural network.....6
2.3 Fuzzy neural network learning algorithm.....9

3. Chip design of fuzzy neural network.....12
3.1 Reconfiguration in hardware FNN.....13
3.2 Processing element architecture in learning unit.....16
3.3 Parallel processing element architecture.....18
3.4 Look up table.....20
3.4.1 Determine the look up table size.....20
3.4.2 Exponential function.....21
3.4.3 Square root function.....22
3.5 Introduction overall control unit function.....24
3.5.1 Configurable setting element.....25
3.5.2 Data flow control element.....26
3.5.3 Address control element.....28

4. Experiments.....29
4.1 Human face recognition and simulation result.....30
4.2 Recognition of Six Dots Braille.....32
4.3 Recognition of Six Dots simulation results.....35

5. Implementation Results.....40
5.1 Cell-Based IC Design Flow.....40
5.2 Chip design and specification.....42

6. Conclusion.....45

Bibliography.....46
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