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研究生:陳威仁
研究生(外文):Chen, WeiJen
論文名稱:19-29 GHz CMOS 接收機前端電路與八位元類比數位轉換器之設計與實現
論文名稱(外文):Design And Implementation Of 19-29 GHz CMOS Receiver Front-End And A 8 Bit Analog-To-Digital Converter
指導教授:林佑昇林佑昇引用關係黃育銘
指導教授(外文):Lin, YoShengYu-Ming Huang
口試委員:林佑昇黃育銘梁效彬
口試委員(外文):Lin, YoShengHuang,YuMingLiang, ShiauBin
口試日期:2012-07-23
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:65
中文關鍵詞:低雜訊放大器、逐漸趨近式類比數位轉換器、前端電路、共振雜散電容
外文關鍵詞:Low Noise Amplifier, Successive Approximation Register Analog-to-Digital Converter, Front end, Resonance stray capacitance
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本論文以CMOS製程實現接收機之前端電路,共分為兩大部分:應用於接收機19~29GHz之低雜訊放大器與一8位元類比數位轉換器的電路模擬與與實現。

第一部分為應用在19~29GHz的低雜訊放大器,利用台積電0.18μm CMOS製程技術來實現。本研究第一級電路使用Common Source的放大器結構,其目的為提供低頻的增益以及寬頻的匹配網路,適當選擇電晶體及傳輸線,可調整其gain的平坦度以及S11的匹配,且也與雜訊的高低有很大的關係;此LNA特色就是在第二級CasCode的電晶體M2及M3中間加入了電感L4,由於Cascode本身寄生電容會影響電路特性以及頻寬不足於是學生使用L4來共振雜散電容,使得增益以及平坦度有所提升。量測結果:在19~29GHz頻帶中S11 的耗損在-5~-16dB,S22耗損皆在-7以下,在S21增益方面為8.63±0.21dB,原因是在輸入端由於傳輸線匹配不合以至於S11損耗在-10以上;此電路消耗功率為8.49mW。

第二部分為一8位元類比數位轉換器,此電路同時也是利用台積電0.18μm CMOS製程技術來實現。此ADC設計為一8bit輸出,雙時脈輸入,弦波訊號由取樣保持電路輸入而保持取樣電路採用SAR端的重置時脈,位移暫存器產生的時脈調節取樣與保持的時間,保持輸出訊號在比較器一端維持一直流電壓而比較器另端為系統回授訊號來自DAC的訊號,時脈控制來自4個flip-flop電路產生除16的時脈,單一flip-flop為一個除2電路故4個串接可形成除2、4、8、16的電路在由一個and閘將訊號集成一個週期為16的時脈;Dac是採用傳統的電容陣列的架構,在此較特別的是開關陣列採用了 inverter 而非傳統的 transmission gate,這種作法有個好處是可以根據電容大小來決定充電速度, 這是因為在給相同的電壓下,大電容的充電速度一定比小電容的充電速度慢,而這種時間差會造成 sar 或 comparator 的不匹配性,進而影響到 INL/DNL。 因此可利用在大電容時 inverter 的並聯數目多來增加充電速度,而小電容時 inverter 的並聯數目少來降低充電速度,以希望達到大小電容之間的充電速度相同。電路架構由取樣保持電路、比較器電路、緩衝及維持輸出電路、時脈控制電路、邏輯控制電路、數位類比轉換器電路。此一8位元逐漸趨近式類比數位轉換器輸入為3kHz的訊號時脈為1MHz。

In this thesis, we using CMOS process to implement receiver front-end circuit, and divided into two part: a 19~29GHz Low Noise Amplifier applied to receiver system and an 8-bit Analog-to-Digital Converter simulation and implement.

The first part is a 19~29GHz Low Noise Amplifier applied to receiver system, and we use 0.18μm CMOS technology provided by TSMC. In this study, the first stage circuit uses the Common Source amplifier structure, which aims to provide low-frequency gain and broadband matching network. Appropriate choice of the transistor and transmission line will adjust its gain flatness and S11 match, and also have a great relationship with the level of noise. The characteristics of this LNA is the second stage, we using a cascode structure and joined a inductor L4 between M2 and M3, because of Cascode itself parasitic capacitance will affect the circuit characteristics, as well as insufficient bandwidth so we use L4 to resonance stray capacitance, it could improve gain and flatness. Measurement results: at 19 ~ 29GHz S11 is -5 ~-16dB, S22 are less than -7 and the gain is 8.63 ± 0.21dB, reason for S11 higher than -10 is the transmission at the input had not matching well; this circuit power consumption is 8.49mW.

The second part is an 8-bit analog to digital converter, this circuit is also using 0.18μm CMOS process technology provided by TSMC. The ADC is designed for an 8 bit output, dual time clock input, the sinusoidal signal from sample and hold input and maintaining for system working is controlled from SAR reset clock, the shift-generator produce a series clock to control sampling time and hold signal time, the comparator is differential input, signal is from sample and hold output and DAC output. Clock control from four flip-flop circuit and in addition to 16 clocks, a single flip-flop circuits as an addition to the two so the 4 cascaded to form in addition to the 2, 4, 8, 16, at last we using a AND gate to produce a 16 clock of a period; Dac is the traditional architecture of the capacitor array, in this particular switch array using the inverter instead of the traditional transmission gate, this approach benefit is based on the capacitor size to determine the charge rate, This is because in same voltage, the charging speed of the large capacitor must be slower than small capacitor, and these inaccuracy may cause SAR or comparator matching error to cause INL/DNL, so the large capacitor we could use the number of multi-inverter parallel to increasing charge time, and using less number of multi-inverter parallel to decrease charge time, to make the same time between large and small capacitor charge time. The SAR A/D Converter architecture is constitute by sample and hold circuit, comparator circuit, the buffer and maintain output circuit, the clock control circuit, the logic control circuits, digital-to-analog converter circuit, this 8-bit A/D Converter input signal of 3kHz clock is 1MHz.

Chinese Abstract……………………………………………………………I
English Abstract……………………………………………………………III
Contents……………………………………………………………………VI
List of Figures………………………………………………………………IX
List of Tables……………………………………………………………XII

Chapter 1 Introduction 1
1.1 Motivation……………………………………………………………1
1.2 Thesis Organization…………………………………………………..4

Chapter 2 The 19~29 GHz Low Power LNA in 0.18 mm CMOS Technology 5
2.1 Introduction…………………………………………………………..5
2.2 Transmission Line theory…………….……………………………...8
2.3 Noise in two-stage networks………………………………………...9
2.4 The 19~29 GHz Low Power LNA in 0.18 mm CMOS Technology……………………………………………………………12
2.4.1 Principle of the Circuit Design…………………………….12
2.4.2 Analysis of the Input Matching…………………………….13
2.5 Simulated Result…………………………………………………14
2.6 Measured Results and Discussion…………………………………..20
2.7 Conclusion…………………………………………………………25

Chapter 3 Fundamental of Analog-to-Digital Converter
27
3.1 Basic concept of Analog-to-Digital Converter……………………...27
3.2 Resolution…………………………………………………………..28
3.3 Signal to Noise Ratio………………………………..………………29
3.4 Signal to Noise Ratio and Distortion Ratio (SNDR).….……………30
3.5 Effective Number Of Bits………………………………………….31
3.6 Offset Error…………………………………..……………………31
3.7 Gain Error……………………………………….………………......32
3.8 Differential Nonlinearity Error………………….……………......32
3.9 Integral Nonlinearity Error…………………….……………......33
3.10 Each type of Analog-Digital Converter……….……………......34
3.10.1 Flash Analog-Digital Converter………………………….34
3.10.2 Pipeline Analog-Digital Converter……………………….35
3.10.3 Successive Approximation Register Analog-Digital Converter…………………………………………………37




Chapter 4 Implementation of Analog-to-Digital Converter
39
4.1 Motivation…….……………………………………………………39
4.2 The Architecture of Successive Approximation A/D Converter……………………………………………………………….40
4.2.1 Sample and Hold…………………………………………....41
4.2.2 A Rail-to-Rail Comparator…………………………………42
4.2.3 Successive Approximation Register…………………………44
4.2.4 Digital-to-Analog Converter…………………………………46
4.3 Simulation Results……...…………………………………………...47
4.3.1 Sample and Hold Simulation Result………………………....47
4.3.2 Comparator Simulation Result……………………………....48
4.3.3 Time Control Simulation Result…………………………....49
4.3.4 Functional Simulation Result……………………………....51
4.4 Chip Layout Considerations…..…………………………………..52
4.5 Chip Measured Considerations………….………………………....55

Chapter 5 Conclusions 57
References………………………………………………………………59 Appendix…………….….………………………………………………62
Vita………………………….…………………………………………65

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[2] http://www.maxim-ic.com/app-notes/index.mvp/id/1023

[3] D. Barras, F. Ellinger, H. Jackel, and W. Hirt, “A low supply voltage SiGe LNA for Ultra-Wideband frontends,” IEEE Microwave And Wireless Components Letters, vol. 14, no. 10, pp. 469-471, Oct. 2004.

[4] Adaptive_Cruise_Control_Sys_Overview.pdf

[5] D. Barras, F. Ellinger, H. Jackel, and W. Hirt, “A low supply voltage SiGe LNA for Ultra-Wideband frontends,” IEEE Microwave And Wireless Components Letters, vol. 14, no. 10, pp. 469-471, Oct. 2004.

[6] Guillermo Gonzalez, “Microwave Transistor Amplifiers Analysis and Design,” Prentice-Hall, Inc., 1984


[7] To-Po Wang Member.“A Low-Voltage Low-Power K-band CMOS LNA Using DC-Current-Path Split Technology” IEEE MICROWAVE AND WIRELESS COMPONENTS LETTER, VOL 20, NO.9,pp 519-521, Sep. 2010

[8] Mohamed El-Nozahi, Student Member, IEEE, Edgar Sanchez-Sinencio, Fellow, IEEE, and Karmran Entesari, Member,IEEE “A Millimeter-Wave(23-32GHz) Wideband BiCOMS Low-Noise Amplifier” IEEE JOUENAL OF SOLID-STATE CIRCUITS, VOL.45, NO.2, pp289-299,Feb. 2010.

[9] To-Po Wang, Member, “ A Low-Voltage Low-Power K-Band CMOS LNA Using DC-Current-Path Split Technology” Page(s):519 - 521 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL20,NO 9,pp519-521, Sep. 2010.


[10] Wei-Han Cho; Shawn S. H. Hsu; Membe; “An Ultra-Low-Power 24 GHz Low-Noise Amplifier Using 0.13 um CMOS Technology” Page(s):681 - 684 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL20,NO 12,pp 681-683, Dec. 2010.

[11] V. Jain; S. Sundararaman; P. Heydari; “A CMOS 22–29 GHz receiver front-end for UWB automotive pulse-radars,” IEEE Trans. Microw Theory Tech, vol. 57, no. 8, pp. 1903–1914, Aug. 2009

[12] Alfi Moscovici "High Speed A/D Converters", Kluwer Academic Publishers 2000


[13] Keh-La, ArminKemna, BedrichcJ. Hosticka, "Modular Low-Power, High Speed CMOS Analog-to-Digital Converter for Embedded System", Kiuwer Academic Publishers. 2003.

[14] Phillip E. Allen and Douglas R. Holberg,"CMOS Analog Circuit Design", Oxford, 2002.

[15] http://www.edn.com/article/475552-What_does_the_ADC_SNR_mean_.php

[16]http://www.eetimes.com/design/microwave-rf-design/4019090/The- differential-signal-advantage-for-communications-system-design

[17] Sung-Min Chin; Chih-Cheng Hsieh; Chin-Fong Chiu; Hann-Huei Tsai "A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application" Circuits and Systems (ISCAS), Proceedings of IEEE International Symposium, pp.1575-1578, May 30, June 2 2010


[18] 陳永親,21~24GHz 汽車雷達系統之CMOS超寬頻接收機前端設計與實現,國立暨南國際大學電機工程所碩士論文,民國一OO年

[19] 王秋瑄,24GHz 射頻接收機前端電路之設計與實現,國立暨南國際大學電機工程所碩士論文,民國九十九年

[20] 黃顥中,應用於射頻系統之UWB CMOS低雜訊放大器及K Band前端電路之設計與實現,國立暨南國際大學電機工程所碩士論文,民國九十九年

[21] 許哲豪,使用單一參考電壓的12位元全叉動切換電容逐漸趨近式類比數位轉換器,國立成功大學電機工程所碩士論文,民國九十二年

[22] 黃冠穎,有效利用能量的逐漸趨近式類比數位轉換器設計,國立成功大學電機工程所碩士論文,民國九十六年

[23] 楊澤龍,應用於微刺激系統之電流自我校正八位元逐漸趨近式類比數位轉換器,國立中正大學電機工程所碩士論文,民國九十四年

[24] 鐘鴻儀,十位元連續漸進式漸進式類比數位轉換器,國立暨南國際大學電機工程所碩士論文,民國九十九年

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