臺灣博碩士論文加值系統

本論文提出並且實作集中算術邏輯單元 (Arithmetic Logic Unit, ALU) 應用在支援 Long Term Evolution (LTE) 和 IEEE 802.11 TGac 長期演進技術接收機無線通訊處理平台。此運算系統透過 share bus 平行接收通訊演算法模組關鍵運算指令，提供19種指令集包括基本運算、浮點數、複數、浮點複數、開平方根、排序和反矩陣等通訊演算法常用的運算。由於無線通訊系統需要大量的運算，電路內的算術單元必須透過平行處理和管線架構來增加運算的吞吐量。使用硬體描述語言 Verilog 實作運算系統架構，並且提供足夠的擴展空間以降低未來系統的設計成本。
此算術邏輯單元可在同一時間內處理多條指令，並且避免結構危障的發生。為了能更快獲得一個指令的運算結果，可將此指令分成多個相同的指令平行處理。若是多條不同的指令平行運算，可以增加指令的吞吐量。另一方面，將指令的資料路徑分成多階段是為了運算連續的資料並且不會產生暫停而必須將資料儲存。可重組的運算架構能讓多個指令共享運算器，降低硬體使用成本，並且未來能在不改變架構的情況下變更運算器或運算指令。

This thesis is proposed to the centralized Arithmetic Logic Unit (ALU) for Wireless Processing Unit (WPU) supporting Long Term Evolution (LTE) and IEEE 802.11 TGac. This architecture parallel receive instruction of algorithm modules through the share bus and support 19 instruction set that communication algorithm common use including basic operation, floating point, complex, complex floating point, square root, sort and inverse matrix etc. With computation-intensive requirement for wireless communication system, the functional units need to work through parallel processing and pipeline architecture to increase the computing throughput. Architecture of ALU is implemented by hardware description language as Verilog, all circuits are implemented by standard-cell. This architecture can change or add computing operations to reduce design cost.
The proposed ALU system can process more than one instruction at the same time, in addition, it avoid structure hazard occurring. One instruction can be divided into many parts for obtaining the result of this instruction faster or processing the multiple different instructions in parallel to get more instruction results. On the other hand, instruction data path is separated into many stages for computing continuous data without stall. The reconfigurable computing architecture is that the variety of instructions can share operations for reducing hardware cost. In addition, it is flexible to add or delete operation/instruction opcode in the future.

摘 要 i
Abstract ii
誌 謝 iii
Table of Contents iv
List of Figure v
List of Table vi
Chapter 1 Introduction 1
Chapter 2 System Overview 3
2.1 Wireless Processing Unit Description 3
2.2 Motivation and Problem Statement 4
Chapter 3 Reconfigurable ALU with Pipeline Architecture 6
3.1 Block Diagram of Reconfigurable ALU 6
3.2 Flow of Reconfigurable ALU Procedures 8
3.3 Parallel Instruction Processing 10
3.3.1 Instruction Format 10
3.3.2 Instruction Processing 12
3.4 Reconfigurable and Pipeline Computing Architecture 14
3.4.1 RALC with Pipeline Architecture 15
3.4.2 Pipeline Matrix Invertor 21
Chapter 4 The Comparison of Reconfigurable ALU 26
4.1 Parallel Processing 26
4.2 RALC 28
4.3 Computing Pipeline Architecture 30
4.4 Summary 33
Chapter 5 Conclusion and Future Works 34
Bibliography 35

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