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研究生:温晨意
研究生(外文):Wen, Cheng-Yi
論文名稱:提前垃圾回收:改善多通道固態硬碟內部平行度之技術
論文名稱(外文):Garbage-Collection Forwarding: A Technique for Improving Internal Parallelism of Multichannel SSDs
指導教授:張立平張立平引用關係
指導教授(外文):Chang, Li-Ping
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊科學與工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:22
中文關鍵詞:固態硬碟快閃記憶體多通道
外文關鍵詞:Solid-state disksFlash memoryMultichannel architectures.
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Solid-state disks use multichannel architectures to boost their data transfer rates. Because realistic disk workloads have numerous small write requests, modern flash-storage devices adopt a write buffer and a set of independent channels for better parallelism in serving small write requests. When a channel is undergoing garbage collection, it stops responding to inbound write traffic and accumulates page data in the write buffer. This results in contention for the buffer space and creates idle periods in channels. This study presents a channel management strategy, called garbage-collection forwarding, to utilize idle channel cycles with garbage collection and restore the balance of buffer-space utilization among channels. The key idea is to increase the overlap among garbage-collection activities in different channels. This study further introduces cycle fling, which is a version of garbage-collection forwarding tailored for the operation model of flash planes. Both techniques are compatible with hybrid mapping and page-level mapping. Experimental results show that the proposed methods greatly outperformed existing designs of multichannel systems in terms of the average number of write requests completed per second (IOPS). We also successfully implemented the proposed methods in a real solid-state disk and proved their feasibility in real hardware.
Solid-state disks use multichannel architectures to boost their data transfer rates. Because realistic disk workloads have numerous small write requests, modern flash-storage devices adopt a write buffer and a set of independent channels for better parallelism in serving small write requests. When a channel is undergoing garbage collection, it stops responding to inbound write traffic and accumulates page data in the write buffer. This results in contention for the buffer space and creates idle periods in channels. This study presents a channel management strategy, called garbage-collection forwarding, to utilize idle channel cycles with garbage collection and restore the balance of buffer-space utilization among channels. The key idea is to increase the overlap among garbage-collection activities in different channels. This study further introduces cycle fling, which is a version of garbage-collection forwarding tailored for the operation model of flash planes. Both techniques are compatible with hybrid mapping and page-level mapping. Experimental results show that the proposed methods greatly outperformed existing designs of multichannel systems in terms of the average number of write requests completed per second (IOPS). We also successfully implemented the proposed methods in a real solid-state disk and proved their feasibility in real hardware.
1 Introduction 1
2 Problem Formulation 3
2.1 Flash-Translation Laye 3
2.2 Multichannel Architectures 4
2.3 Buffer-Space Contention 5
3 Channel Management 6
3.1 Channel Binding and Write Buffering 6
3.2 Garbage-Collection Forwarding 7
3.3 Preemption of Garbage Collection 9
3.4 Cycle Filling 10
3.4.1 Cycle Filling with Hybrid Mapping 10
3.4.2 Cycle Filling with Page Mapping 12
3.5 Flash Planes and Hybrid Architectures 12
4 Experimental Results 14
4.1 Experimental Setup and Performance Metrics 14
4.2 Multichannel Architectures 15
4.3 Write Buffer Size and Multi-Plane Commands 17
4.4 Case Study: A GP5086-based SSD 19
5 Conclusion 20
Bibliography 20
[1] Nitin Agrawal, Vijayan Prabhakaran, Ted Wobber, John D. Davis, Mark Manasse, and Rina Panigrahy. Design tradeoffs for SSD performance. In ATC’08: USENIX 2008 Annual Technical Conference on Annual Technical Conference, pages 57–70. USENIX Association, 2008.
[2] Li-Pin Chang. A hybrid approach to nand-flash-based solid-state disks. Computers, IEEE Transactions on, 59(10):1337 –1349, oct. 2010.
[3] Li-Pin Chang and Tei-Wei Kuo. An adaptive striping architecture for flash memory storage systems of embedded systems. In 8th IEEE Real-Time and Embedded Technology and Applications Symposium, pages 187–196, 2002.
[4] L.P. Chang and Y.C. Su. Plugging versus logging: A new approach to write buffer management for solid-state disks. In Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pages 23–28. IEEE, 2011.
[5] Cagdas Dirik and Bruce Jacob. The performance of pc solid-state disks (ssds) as a function of bandwidth, concurrency, device architecture, and system organization. In Proceedings of the 36th annual international symposium on Computer architecture, ISCA ’09, pages 279–289, New York, NY, USA, 2009. ACM.
[6] Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. Dftl: a flash translation layer employing demand-based selective caching of page-level address mappings. In ASPLOS ’09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems, pages 229–240. ACM, 2009.
[7] Jeong-Uk Kang, Jin-Soo Kim, Chanik Park, Hyoungjun Park, and Joonwon Lee. A multi-channel architecture for high-performance NAND flash-based storage system. J. Syst. Archit., 53(9):644–658, 2007.
[8] Sooyong Kang, Sungmin Park, Hoyoung Jung, Hyoki Shim, and Jaehyuk Cha. Performance trade-offs in using nvram write buffer for flash memory-based storage devices. Computers, IEEE Transactions on, 58(6):744 –758, jun. 2009.
[9] Hyojun Kim and Seongjun Ahn. Bplru: a buffer management scheme for improving random writes in flash storage. In FAST’08: Proceedings of the 6th USENIX Conference on File and Storage Technologies, pages 1–14, Berkeley, CA, USA, 2008. USENIX Association.
[10] Sang-Won Lee, Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon Park, and Ha-Joo Song. A log buffer-based flash translation layer using fully-associative sector translation. Trans. on Embedded Computing Sys., 6(3):18, 2007.
[11] Micron Technology, Inc. MT29F512G08 NAND Flash Memory Data Sheet, 2009.
[12] Eyee Hyun Nam, B.S.J. Kim, Hyeonsang Eom, and Sang Lyul Min. Ozone (o3): An out-of-order flash memory controller architecture. Computers, IEEE Transactions on, 60(5):653 –666, may 2011.
[13] Open NAND Flash Interface. ONFi 3.0 Specification, 2011.
[14] Open Source Development Lab. Iometer. http://http://www.iometer.org/, 2003.
[15] Seung-Ho Park, Jung-Wook Park, Shin-Dug Kim, and Charles C. Weems. A pattern adaptive nand flash memory storage structure. Computers, IEEE Transactions on, 61(1):134 –138, jan. 2012.
[16] S.K. Park, Y. Park, G. Shim, and K.H. Park. Cave: channel-aware buffer management scheme for solid state disk. In Proceedings of the 2011 ACM Symposium on Applied Computing, pages 346–353. ACM, 2011.
[17] Samsung Electronics Company. K9MDG08U5M 4G * 8 Bit MLC NAND Flash Memory Data Sheet, 2008.
[18] Yoon Jae Seong, Eyee Hyun Nam, Jin Hyuk Yoon, Hongseok Kim, Jin-Yong Choi, Sookwan Lee, Young Hyun Bae, Jaejin Lee, Yookun Cho, and Sang Lyul Min. Hydra: A block-mapped parallel flash memory solid-state disk architecture. IEEE Transactions on Computers, 59:905–921, 2010.

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