臺灣博碩士論文加值系統

無線近身網路是專門用來蒐集監測身體訊號以提供可靠的生理資訊。為了達到長時間的連續醫療照護監測，可靠的訊號傳輸、低功耗、微小化為無線近身網路設計的基本需求。
本論文提出一個具有兩種調變之基頻收發器，其調變方式包含了多音分碼多工與正交分頻多工兩種，以分別因應多使用者共存(可允許8個使用者同時使用)以及某些需要高資料傳輸率的應用需求。基於對於無線近身網路系統行為的分析，本論文提出相對應的低功耗技術，例如:提高資料傳輸率、用於生理訊號儲存的記憶元件設計最佳化、以及其他低功耗的硬體實現等。另一方面，為了達到系統整合的微小化，本論文也提供一個可調相位頻率的時脈產生器與頻率預先補償技術來提高系統對於頻率誤差的容忍度(可提高至100 ppm )，以供未來系統整合當中，取代傳統用來提供時脈之石英震盪器。而所提出的基頻收發器晶片組已由90奈米標準CMOS製程實現，此晶片組可操作在0.5伏特，並提供最高4.85 Mbps的傳輸速度，且調變器的功耗僅有5.52 μW。
由系統的功耗分析，無線傳輸模組的功耗占最大比例的系統平均功耗，尤其是前端射頻的功率放大器電路。由於採用多載波調變之訊號的震幅變化範圍較大，在避免訊號失真的考量之下，功率放大器的效率大幅地降低。因此，本論文介紹LINC (Linear amplification by nonlinear components) 技術來改善功率放大電路之效率，其概念為將原本具有相位與震幅調變的訊號利用訊號成分分解器分解成兩路僅帶有相位資訊的訊號，此兩路訊號即可使用高效率非線性放大器來放大，接著將兩路放大後的訊號相加，即可還原我們想到的訊號。此論文特別專注在訊號成分分解器之設計，我們採用全數位相位調變式的實現架構來避免高速數位類比轉換器以及正交調製器的使用，另外，本論文也提出一個兩路偏差校正的機制並整合於訊號成分分解器中以減輕前端高頻電路的設計複雜度。此訊號成分分解器以90奈米標準CMOS製程晶片實現，藉由低複雜度的電路設計與低功耗技術，此訊號成分分解器操作在中頻100 MHz，其功耗小於1 mW，另外此設計也可提供0.02 dB增益與0.15度相位補償精準度，大幅減輕前端高頻電路的設計負擔。
本論文也更進一步介紹LINC技術的進階效能改良技術-非對稱多階LINC (Uneven multi-level LINC, UMLINC)，用來減少兩路訊號相加時造成的功耗浪費，此技術需要功率放大器提供兩種不同的增益，但系統的放大效率可由原本LINC的13.08%大幅改善至44.82%。然而，兩路偏差的問題在不同放大器增益模式下也變得更加複雜，本論文也提出改良的訊號分解方法，可以將兩路偏差的問題在訊號分解過程中補償。為了用於非對稱多階LINC系統，進階的訊號成分分解器使用相同的製程完成晶片實現與驗證，可根據輸入訊號震幅動態的提供放大器增益控制，並同時產生對應的相位調變訊號，利用低功耗技術與電路設計，此設計功耗為0.65 mW，採用非對稱多階LINC技術搭配本論文提出的低功耗訊號成分分解器，整體無線傳輸模組的功耗可減少80.23%。應用於提出的無線近身網路應用中，多音分碼多工模式的系統平均功耗可由原來的1626 μW下降至518 μW，當採用正交分頻多工模式時，系統平均功耗也可由211 μW 減至 132 μW。

Wireless body area network (WBAN) is an emerging technology which is specifically designed for body signal collection and monitoring to provide reliable physical information. In order to achieve long duration monitoring for biotelemetry applications, the WBAN system is required to provide reliable signal transmission, ultra-low power operation, and highly integrated tiny area for comfortable purposes.
This dissertation first introduces a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5x of state-of-the-art systems). The baseband transceiver chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 ?巰.
From the system power analysis, the power dominant of the proposed WBAN solution is the active power of the wireless transmission link, especially the power amplifier (PA) due to the poor efficiency. Accordingly, linear amplification by nonlinear components (LINC) is introduced to improve the amplifier efficiency. The basic concept is to separate the original phase-and-amplitude modulated signal into two phase-only-modulated signals, then these two signals can be amplified by high-efficiency nonlinear PAs. Then the desired signal can be reconstructed by combining these two amplified signals. This dissertation focuses on the signal component separator (SCS) design. An all-digital phase-modulated SCS architecture, including the phase calculation DSP and a digitally-control phase shifter (DCPS) pair, is proposed in this work to avoid the usage of DACs and quadrature modulators. Besides, this SCS design also considers the branch mismatch issue and presents a digital mismatch detection and compensation scheme, which can be integrated in the SCS without increasing the front-end circuit complexity. The proposed SCS design is manufactured in 90 nm standard CMOS process. The overall SCS operating at maximum 100 MHz consumes less than 1 mW which minimizes the power overhead of the LINC transmitter, and it further provides a 0.02 dB gain and 0.15o phase fine-tune resolution to release the front-end design complexity.
Besides, the uneven multi-level LINC (UMLINC) is introduced for further efficiency improvement. Assuming the PA can provide dual gain mode, the efficiency can be improved from 13.08% to 44.82% (3.44x improvement comparing to LINC). The branch mismatch consideration is also considered during the region boundaries decision of the signal separation. An all-digital SCS chip, which provides the PA gain controls and corresponding phase-modulated signals for UMLINC systems, is manufactured in 90 nm standard CMOS process. By applying the voltage scaling and low power techniques, the power cost of UMLINC SCS is only 0.65 mW. With the proposed UMLINC SCS, 80.23% transmitter power can be reduced comparing to conventional transmitter with a linear PA. Applying this technique to the proposed WBAN system, the average system power can be reduced from 1626 μW to 518 μW for MT-CDMA mode and from 211 μW to 132 μW for OFDM mode respectively.

摘要 i
Abstract iii
誌謝 vi
Table of Contents vii
List of Figures xi
List of Tables xvi
Chapter 1: Introduction 1
1-1 Introduction to WBAN 1
1-2 Proposed System Specifications 4
1-3 Transmission Energy Analysis and Low Power Strategies 8
1-4 Goal and Contributions 10
1-5 Organization 13
Chapter 2: Dual-Mode Baseband Transceiver 15
2-1 System Operation and Baseband Modulation 15
2-2 Optimal Storage Unit Decision 18
2-2.1 Power Analysis and Size Decision 18
2-2.2 SU Design for WBAN 19
2-3 Tiny Area Integration 21
2-3.1 RSD Based Pre-calibration Scheme 21
2-3.2 Mismatch Estimation Method 22
2-3.3 PFTCG Design 24
2-4 Baseband Transceiver Chip Implementations 25
2-4.1 Voltage Scaling 26
2-4.2 Power Gating 28
2-5 System Performance Evaluation 29
2-5.1 System Power Estimation and Coexistence 29
2-5.2 System Power with Voltage Scaling 31
2-5.3 System Performance with Frequency Mismatch 32
2-6 Summary 34
Chapter 3: LINC Signal Component Separator 35
3-1 Motivations 35
3-1.1 PAPR Analysis 35
3-2 LINC Background and Overview 38
3-2.1 LINC Basic Principle 38
3-2.2 LINC Architecture with Different SCS Topologies 40
3-2.3 Design Challenges 43
3-3 Proposed SCS Architecture 46
3-4 Branch Mismatch Calibration 47
3-4.1 Mismatch Model and Effects 47
3-4.2 Mismatch Detection Scheme 54
3-4.3 Mismatch Compensation Scheme 59
3-4.4 Performance Evaluations 64
3-5 Efficiency Enhancement Techniques 70
3-5.1 Average Efficiency Analysis 70
3-5.2 Average Efficiency Enhancement Techniques 73
3-5.3 UMLINC with Branch Mismatch Issues 82
3-5.4 Performance Evaluation 85
3-6 LINC SCS Chip Implementation 87
3-6.1 Power Domain Partitions and Voltage Scaling 88
3-6.2 Phase Calculator 89
3-6.3 Phase Modulator Pair 91
3-6.4 Codeword Mapper 93
3-6.5 Parameter Detection Scheme – Pre-calibration Scheme 94
3-7 UMLINC SCS Chip Implementation 96
3-7.1 Multi-Level Phase Calculator 97
3-7.2 Modified Phase Modulator Pair with BSG Scheme 99
3-7.3 Parameter Detection Scheme – Continuous PVT Monitor 100
3-8 Summary 102
Chapter 4: Chip Implementation Results & Performance Evaluations 104
4-1 Baseband Chip Implementation Results 105
4-1.1 Chipset Summary 105
4-1.2 Measurement Results 106
4-2 LINC SCS Chip Implementation Results 110
4-2.1 Chip Summary 110
4-2.2 Measurement Results 111
4-2.3 Comparisons to Related Works 116
4-3 UMLINC SCS Chip Implementation Results 117
4-3.1 Chip Summary 117
4-3.2 Measurement Results 119
4-3.3 Comparisons 123
4-4 System Power Evaluations 124
4-4.1 Amplification Blocks Power Reductions 124
4-4.2 WBAN Average System Power Reductions 126
4-4.3 Comparisons to the Related Works 128
Chapter 5: Conclusion and Future Work 130
5-1 Conclusion 130
5-2 Future Work 131
Reference 133
Appendix1: ECG Monitoring System Prototype 138

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