|
[1] S. Koester, A. Young, R. Yu, S. Purushothaman, K. N. Chen, D. La Tulipe, N. Rana, L. Shi, M. Wordeman, and E. Sprogis, "Wafer-level 3D integration technology," IBM Journal of Research and Development, vol. 52, pp. 583-597, 2008. [2] R. S. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs," Proceedings of the IEEE, vol. 94, pp. 1214-1224, Jun. 2006. [3] A. Topol, D. C. L. Tulipe, L. Shi, D. Frank, K. Bernstein, S. Steen, A. Kumar, G. Singco, A. Young, and K. Guarini, "Three-dimensional integrated circuits," IBM Journal of Research and Development, vol. 50, pp. 491-506, 2006. [4] S. Das, A. Fan, K. N. Chen, C. S. Tan, N. Checka, and R. Reif, "Technology, performance, and computer-aided design of three-dimensional integrated circuits," in Proceeding on ISPD 2004, pp. 108-115. [5] C. T. Ko, Z. C. Hsiao, H. C. Fu, K. N. Chen, W. C. Lo, and Y. H. Chen, "Wafer-to-wafer hybrid bonding technology for 3D IC," in Proc. ESTC, Berlin, Sept. 2010, pp. 1-5. [6] P. Morrow, C. M. Park, S. Ramanathan, M. Kobrinsky, and M. Harmes, "Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology," Electron Device Letters, IEEE, vol. 27, pp. 335-337, 2006. [7] P. Benkart, A. Munding, A. Kaiser, E. Kohn, A. Heittmann, H. Huebner, and U. Ramacher, "Three-dimensional integration scheme with a thermal budget below 300° C," Sensors and Actuators A: Physical, vol. 139, pp. 350-355, 2007. [8] M. Chang, W. Wu, C. Lin, P. Chiu, M. Chen, Y. Chen, H. Lai, Z. Lin, S. Sheu, and T. Ku, "A Larger Stacked Layer Number Scalable TSV-based 3D-SRAM for High-Performance Universal-Memory-Capacity 3D-IC Platform," in Symposium on VLSI Circuits Kyoto, Japan,, Jun. 2011, pp. 13-15. [9] N. Ranganathan, K. Prasad, N. Balasubramanian, and K. Pey, "A study of thermo-mechanical stress and its impact on through-silicon vias," Journal of Micromechanics and Microengineering, vol. 18, p. 075018, 2008. [10] C. T. Ko, Z. C. Hsiao, Y. J. Chang, P. S. Chen, Y. J. Hwang, H. C. Fu, J. H. Huang, C. W. Chiang, S. S. Sheu, and Y. H. Chen, "A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application," IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, vol. 12, p. 209, 2012. [11] K. N. Chen, S. H. Lee, P. S. Andry, C. K. Tsang, A. W. Topol, Y. M. Lin, J. Q. Lu, A. M. Young, M. Ieong, and W. Haensch, "Structure, design and process control for Cu bonded interconnects in 3D integrated circuits," in IEDM Tech. Dig., San Francisco, CA, Dec. 2006, pp. 367-370. [12] R. Yu, F. Liu, R. Polastre, K. N. Chen, X. Liu, L. Shi, E. Perfecto, N. Klymko, M. Chace, and T. Shaw, "Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding," in IEDM Tech. Dig., San Francisco, CA, Dec. 2009, pp. 170-171. [13] T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, "New three-dimensional integration technology using self-assembly technique," in IEDM Tech. Dig., San Francisco, CA, Dec. 2005, pp. 348-351. [14] F. Liu, R. Yu, A. Young, J. Doyle, X. Wang, L. Shi, K. N. Chen, X. Li, D. Dipaola, and D. Brown, "A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding," in IEDM Tech. Dig., San Francisco, CA, Dec. 2008, pp. 1-4. [15] J. Q. Lu, "3-D hyperintegration and packaging technologies for micro-nano systems," Proceedings of the IEEE, vol. 97, pp. 18-30, Jan. 2009. [16] P. Svasek, E. Svasek, B. Lendl, and M. Vellekoop, "Fabrication of miniaturized fluidic devices using SU-8 based lithography and low temperature wafer bonding," Sensors and Actuators A: Physical, vol. 115, pp. 591-599, 2004. [17] P. Abgrall, C. Lattes, V. Conedera, X. Dollat, S. Colin, and A. M. Gue, "A novel fabrication method of flexible and monolithic 3D microfluidic structures using lamination of SU-8 films," Journal of Micromechanics and Microengineering, vol. 16, p. 113, 2006. [18] C. Tan and R. Reif, "Silicon multilayer stacking based on copper wafer bonding," Electrochemical and Solid-State Letters, vol. 8, p. G147, 2005. [19] Y. S. Tang, Y. J. Chang, and K. N. Chen, "Wafer-level Cu-Cu bonding technology," Microelectronics Reliability, 2011. [20] K. Chen, C. Tan, A. Fan, and R. Reif, "Morphology and bond strength of copper wafer bonding," Electrochemical and Solid-State Letters, vol. 7, p. G14, 2004. [21] J. McMahon, E. Chan, S. Lee, R. Gutmann, and J. Q. Lu, "Bonding interfaces in wafer-level metal/adhesive bonded 3D integration," in Proc. 58th ECTC, Lake Buena Vista, FL, Jun. 2008, pp. 871-878. [22] S. Bader, W. Gust, and H. Hieber, "Rapid formation of intermetallic compounds interdiffusion in the Cu---Sn and Ni---Sn systems," Acta metallurgica et materialia, vol. 43, pp. 329-337, 1995. [23] R. Agarwal, W. Zhang, P. Limaye, and W. Ruythooren, "High density Cu-Sn TLP bonding for 3D integration," in Proc. 59th ECTC, 2009, pp. 345-349. [24] H. Liu, K. Wang, K. Aasmundtveit, and N. Hoivik, "Intermetallic Compound Formation Mechanisms for Cu-Sn Solid–Liquid Interdiffusion Bonding," Journal of Electronic Materials, pp. 1-10, 2012. [25] L. Li, J. Jiao, L. Luo, and Y. Wang, "Cu/Sn isothermal solidification technology for hermetic packaging of MEMS," in Nano/Micro Engineered and Molecular Systems, 2006. NEMS '06. 1st 2006, pp. 1133-1137. [26] R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, "Cu/Sn microbumps interconnect for 3D TSV chip stacking," in Proc. 60th ECTC, 2010, pp. 858-863. [27] R. Reif, A. Fan, K. N. Chen, and S. Das, "Fabrication technologies for three-dimensional integrated circuits," 2002, pp. 33-37. [28] F. Bartels, J. Morris, G. Dalke, and W. Gust, "Intermetallic phase formation in thin solid-liquid diffusion couples," Journal of Electronic Materials, vol. 23, pp. 787-790, 1994. [29] Y. Rong, J. Cai, S. Wang, and S. Jia, "Low temperature Cu-Sn bonding by isothermal solidification technology," in International Conference on ICEPT-HDP 2009, pp. 96-98. [30] C. T. Ko and K. N. Chen, "Wafer-level bonding/stacking technology for 3D integration," Microelectronics Reliability, vol. 50, pp. 481-488, 2010. [31] J. McMahon, J. Q. Lu, and R. Gutmann, "Wafer bonding of damascene-patterned metal/adhesive redistribution layers for via-first three-dimensional (3D) interconnect," in Proc. 55th ECTC, Rensselaer Polytech. Inst., Troy, NY, Jun. 2005, pp. 331-336 Vol. 1. [32] C. K. Lee, T. Chang, Y. Huang, H. Fu, J. H. Huang, Z. Hsiao, J. H. Lau, C. T. Ko, R. Cheng, and K. Kao, "Characterization and Reliability Assessment of Solder Microbumps and Assembly for 3D IC Integration," in Proc. 61th ECTC, Lake Buena Vista, FL, Jun. 2011, pp. 1468-1474. [33] K. Chen, A. Fan, C. Tan, and R. Reif, "Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology," Electron Device Letters, IEEE, vol. 25, pp. 10-12, 2004.
|