臺灣博碩士論文加值系統

近年來，「環保綠能、永續生存」是近年來各界發展的重點。對電子產品而言，電池是能量的主要來源，延長電池的壽命可減少電池的消耗；另一方面，使用低功率設計，讓電路能降低功率消耗並延長電池的壽命。根據 P = fCV2 的理論中，同時降低操作電壓、減少電容負載的多重作用下，使得動態功率可達到好幾個羃次方 (Order) 的下降。為了達到低功率的效果，降低操作電壓是最直覺又有效的方法。甚至，有許多研究是將電路操作在近臨界區(Near-threshold)附近或直接在次臨界區裡操作。奈米技術已經廣泛地運用在低功耗的應用上，包括RF、Analog、AD/DA、與MPU等，功率更低的還有生理信號檢測的相關設計。充分利用奈米技術中元件負載減小的特性，以及次臨界區電流的極限。
然而近臨界電路的設計將元件操作在近臨界區，目的是大幅降低功耗，達到所謂的效率能源(Energy-efficient)的特色。但是它有幾個主要的瓶頸：第一、操作速度慢，多應用於生醫晶片或其它慢速的系統。第二、靜態漏電功率消耗的問題在近臨界區下更顯得嚴重。第三、嚴重的製程漂移，影響著良率與量產成本。
在本論文裡，我們提出了近臨界電壓系統單晶片(System on Chip, SoC)上的資料傳輸(Data link)電路設計。並提出一系列全新的靴帶式技術(Bootstrap technique)，解決近臨界區電路設計的問題。我們提出的靴帶式技術，主要概念是使電路可提供雙向的升壓功能，所謂的雙向，是同時對P型跟N型元件作用，一邊大幅地增加驅動力，一邊抑制靜態漏電。相較於傳統電路操作在近臨界區，可以有兩個order的改善。另一個的優點就是靴帶式技術可以使在次臨界區操作電壓下的電路，操作在一般的三極管區 (Triode region)，使得電路模型更加精確。我們從電路的蒙地卡羅分析就可以清楚地了解到製程漂移因此大幅減少。
我們一共呈現了四個相關的電路：(1)一個應用於時脈網路(clock network)裡，可主動減少漏電流之靴帶式反相器。操作在0.2V時，即便是1cm晶片上連線的時脈樹，能提供10MHz的穩定時脈，能加以抑制低電壓操作時嚴重的靜態漏電流。此外，本設計使用閘極升壓(Gate Boosting)的概念，使大部分元件操作在導通區，大幅降低製程漂移。(2)一個應用在晶片匯流排(on-chip bus)上，能有效抑制符號干擾(Inter-Symbol Interference, ISI)的靴帶式中繼器設計，VDD = 0.3V時，單一個channel最高可以傳輸100Mbps的資料傳輸率 (使用210-1 PRBS)，即便在VDD = 0.1V時，仍有0.8Mbps的資料傳輸率。(3)接著，我們尋求最佳的有效能源設計，提出的高倍升壓的中繼器，提供三倍與四倍升壓功能之預驅動器(Pre-driver)來提供最佳的有效能源設計，而不會犧牲操作速度。我們應用在晶片匯流排中的中繼器，僅使用VDD = 0.15V的操作電壓，最高可達到5Mbps的資料傳輸率，每位元的能源消耗僅有35.2fJ。(4)最後，我們提出了靴帶式振盪器(bootstrapped ring oscillator)，並完成了一個可操作在近臨界電壓的全數位鎖位迴路(All-digital PLL, ADPLL)。操作在0.5V時，這個ADPLL可提供480MHz的輸出頻率，僅有78μW的功率消耗，而在0.25V時，仍可提供44.8MHz輸出頻率，消耗2.4μW的功率。

For the sustainable electronic devices, ultra-low power design is essential to prolong the battery lives. According to P = fCV2, scaling the supply voltage down is the most effective way to reduce the power consumption. According to the forecast from the International Technology Roadmap for Semiconductors (ITRS), the supply voltage will be scaled to 0.5V for low-power applications within the next generation. Scaling the supply voltage near the threshold voltage is the most favorable solution for low-power designs. On the other hand, Nano-scaled devices exceed the limit of the speed in the near-threshold region based on small device loading. Nano-scaled process is broadly applied to ultra-low power designs, which includes RF, AD/DA, MPU, especially in biomedical applications. Emerging embedded biomedical applications have once more pushed the low-power designs into another extreme case.
In order to achieve the feature of the energy-efficient operation, the designs are applied to work using near-threshold supply. However, near-threshold circuit design is definitely challenging because the driving capability (Ion), which is limited to apply to slow system. Then, the static leakage power becomes severe, and decreases the Ion/Ioff ratio. Moreover, process variations are degraded significantly, affecting the circuit performance, the power efficiency, and the fabrication yield.
In this dissertation, we propose circuit designs on-chip data link system using near-threshold supply. In order to improve the design issues in the near-threshold region, we have developed several bootstrapped circuits. The main contribution of the proposed bootstrapped techniques is to boost the gate voltage at the both sides, which means to boost the gate voltage of the PMOS and NMOS at the same time. The proposed circuit is applicable in both increasing driving ability by boosting signals into super-threshold region and reducing the leakage current. While the circuit is operated in sub-threshold region, two-order improvement is achieved. In addition, the bootstrapped circuits are operated in triode region with the near-threshold supply. Consequently, that explain why the process variation affects the proposed design scheme to a lesser extent. We can verify it with simulations of Monte Carlo analysis.
Four build blocks using bootstrapped circuits in on-chip data link have been proposed. The first one is a bootstrapped CMOS inverter applied to on-chip clock network. In addition to improving the driving ability, a large gate voltage swing from -VDD to 2VDD suppresses the sub-threshold leakage current. The test chip is able to achieve 10MHz operation under 200mV VDD; the power consumption is 1.01μW. The Monte Carlo analysis results indicate that a sigma of delay time is only 2.9ns at 0.2V operation. Then, an ISI-suppressed bootstrapped repeater applied to on-chip bus is proposed. The bootstrapped CMOS repeaters are inserted to drive a 10mm on-chip bus. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. The measured results demonstrate that for a 10-mm on-chip bus, it can achieve 100Mbps data rate at 0.3V, and even 0.8 Mbps at 0.1V. The third section investigates the performance of the interconnects with repeater insertion in the sub-threshold region. A 3X CMOS pre-driver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. The measured results show that the 3X (4X) pre-drivers can achieve 5Mbps (1.5Mbps) data rate at 0.15V with an efficiency of 35.2fJ (32.8fJ). The last section, we present a near-threshold supply ADPLL with bootstrapped digitally-controlled ring oscillator (BDCO) that allows an ADPLL to operate with a near-threshold supply. The BDCO is composed of a bootstrapped ring oscillator (BTRO) and a weighted thermometer-controlled resistance network (WTRN). The proposed bootstrapped delay cell generates large gate voltage swing to improve the driving capability significantly. The boosted output swing keeps the transistors operated in the linear region to provide high linearity of the output frequency as function of VDD even using a near-threshold supply. According to the transferring character of the BTRO, WTRN provides linear control while sweeping the supply voltage. The proposed ADPLL oscillates from 36.8 to 480MHz with a power consumption of 2.4-78μW under a supply voltage of 0.25-0.5V.

摘要 iii
ABSTRACT v
Table of Contents ix
Chapter 1 Introduction 1
1.1. Challenges in Nano-Scaled Near-threshold Design 1
1.2. Near-threshold On-chip Data Link 2
1.3. Organization of the Dissertation 3
Chapter 2 Background Review 4
2.1. Effects in Nano-scaled Process [6] 4
2.1.1. Short-Channel Effect 4
2.1.2. Narrow-Width Effect 5
2.1.3. Sub-threshold Leakage [6, 9] 6
2.1.4. Drain-Induced Barrier Lowering [6] 6
2.1.5. Gate-Induced Drain Leakage [6, 10] 7
2.1.6. Gate Leakage [11] 7
2.2. Challenges in Ultra Low-voltage Designs 8
2.2.1. Degradation of Driving Capability 8
2.2.2. Leakage Power and Ion-to-Ioff Ratio [8, 12] 8
2.2.3. Process, Voltage and Temperature Variation 9
2.3. Low-voltage Design Techniques 10
2.3.1. Bootstrap Techniques 10
2.3.2. Dynamic Voltage and Frequency Scaling 12
2.3.3. Multi-threshold MOS Control 13
2.3.4. Bulk-driven Technique 13
2.4. Summary 13
Chapter 3 Near-threshold Clock Network 15
3.1. Overview of On-chip Interconnect 16
3.1.1. RC-Interconnect with repeater insertion 16
3.1.2. Time constant, power dissipation and FoM 17
3.2. Proposed Active Leakage Reduction Bootstrapped Inverter 18
3.3. Detail Evaluation and Discussion 20
3.3.1. Boosting Efficiency 21
3.3.2. Reduction of Leakage Current 22
3.3.3. Delay Time Analysis 25
3.3.4. Delay Time Analysis of Process Variation 27
3.4. Implementation and Experimental Results 28
3.4.1. Implementation of the Bootstrap Capacitor 28
3.4.2. Chip Implementation and Measurement 29
3.5. Summary 31
Chapter 4 Near-threshold On-chip Bus 32
4.1. Proposed On-chip Bus Architecture 32
4.2. ISI-suppressed Bootstrapped Driver 33
4.3. Detailed Evaluation and Comparisons 35
4.3.1. Boosting Efficiency 35
4.3.2. Leakage Current Reduction 36
4.3.3. Leakage Power Analysis 36
4.3.4. ISI Suppression 41
4.3.5. Energy Efficiency 43
4.3.6. Monte Carlo Simulations 45
4.4. Experimental Setup and Measurement 47
4.4.1. Chip implementation 47
4.4.2. Measured Waveforms 48
4.4.3. Leakage Power Measurement 53
4.5. Summary 55
Chapter 5 High-boosting Pre-driver 56
5.1. Proposed High-boosting Pre-driver 56
5.2. High-boosting Pre-driver in Long Interconnects 59
5.2.1. Leakage Current Reduction 59
5.2.2. Energy Efficiency 59
5.2.3. Boosting Efficiency 62
5.2.4. Monte Carlo Simulations 63
5.3. Experiment and Measurement Results 65
5.3.1. Chip implementation 65
5.3.2. Measured Waveforms 66
5.4. Summary 68
Chapter 6 Near-threshold ADPLL 70
6.1. Architecture of Proposed All-Digital PLL 71
6.1.1. PFD, PS and TDC 71
6.1.2. DLF 72
6.1.3. Bootstrapped Digitally-Controlled Oscillator 73
6.1.3.1. Bootstrapped Ring Oscillator 74
6.1.3.2. Weighted-Thermometer Code Control 75
6.1.4. SDM 76
6.2. Detailed Evaluation on BTRO 77
6.2.1. Power Analysis of BTRO 77
6.2.2. Linearity Analysis of BTRO 78
6.3. Experimental Results and Comparisons 81
6.3.1. Chip Implementation 81
6.3.2. Measured Results 83
6.3.3. Comparisons 86
6.4. Conclusions 87
Chapter 7 Conclusions 98
References 98
VITA 98
Publication List 98

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