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研究生:陳逸瑋
研究生(外文):Chen, Yi-Wei
論文名稱:一個快速鎖定460.1MHz至6.177GHz之全數位式鎖相迴路的設計
論文名稱(外文):Design of a Fast-Locking 460.1MHz to 6.177GHz All-Digital Phase Locked Loop
指導教授:洪浩喬
指導教授(外文):Hong, Hao-Chiao
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電控工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:123
中文關鍵詞:全數位式鎖相迴路快速鎖定寬幅調整錯位法
外文關鍵詞:ADPLLFast LockingWide Tuning RangeRegula Falsi
相關次數:
  • 被引用被引用:2
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  • 下載下載:69
  • 收藏至我的研究室書目清單書目收藏:0
  本論文提出了一個可快速鎖定與寬幅調整之全數位式鎖相迴路的設計。在鎖定方式的部分,為了達到快速鎖定的目的,我們將鎖相迴路分為頻率捕捉與相位追蹤兩模式。在頻率捕捉模式下使用了名為Regula Falsi的方式來預測輸出頻率,並且不論數位控制振盪器的線性與否,此方法保證鎖相迴路的頻率一定可以鎖定;在相位追蹤模式則使用了兩種不同的迴路頻寬大小來進行相位鎖定與抖動抑制,第一階段使用較大迴路頻寬來快速的追蹤相位鎖定軌跡,第二階段則使用較小的頻寬,其目的在於降低鎖定後的相位雜訊及抖動。
  本電路已經使用TSMC 90nm CMOS的技術實現,核心面積為0.0646 mm2,而整體晶片面積為0.709 mm2。量測結果顯示頻率部分的鎖定時間為5個參考頻率週期,而相位鎖定的部分則只需3個週期即可完成;鎖相迴路輸出頻率的範圍則為460.1 MHz至6.177 GHz,而峰對峰抖動值的表現部分,在480 MHz的輸出頻率時為1.9% U.I.,在3 GHz的輸出頻率可達到11.7% U.I.,在5 GHz的輸出頻率可達到7.0% U.I.,而在6 GHz的輸出頻率則為5.1% U.I.;在輸出頻率為6 GHz下,相位雜訊為-81.68 dBc/Hz@1MHz與-108.22 dBc/Hz@10MHz。此全數位式鎖相迴路的功率消耗效率為9.2370 mW/GHz。
This thesis presents a design of fast-locking and wide-range all-digital phase locked loop (ADPLL). The locking procedure is partitioned into two modes including the Frequency Acquisition mode and the Phase Tracking mode. In the Frequency Acquisition mode, a novel frequency locking method called Regula Falsi is used for faster frequency locking. No matter the transfer curve of the digitally controlled oscillator (DCO) is linear or not, the method guarantees the frequency can always be locked. In addition, the frequency can be locked within two steps if the DCO has a linear transfer function. In the Phase Tracking mode, the ADPLL adopts two different loop bandwidths. The design first issues a wider loop bandwidth to speed up the phase tracking. After the phase is locked, the loop bandwidth is adjusted to a smaller one to reduce the phase noise and jitter.
The circuit has been implemented in TSMC 90nm CMOS technology. The core area is 0.0646 mm2 and the whole chip area with bonding pads is 0.709 mm2. Measurement results show that the lock-in time of frequency takes 5 cycles and the lock-in time of phase is 3 cycles. The output frequency range is from 460.1 MHz to 6.177 GHz. The pk-pk jitter at 480 MHz output is 1.9% U.I., at 3 GHz output is 11.7% U.I., at 5 GHz output is 7.0% U.I., and at 6 GHz output is 5.1% U.I. Under the 6 GHz output frequency, the phase noise at 1 MHz offset is -81.68 dBc/Hz and at 10 MHz offset is -108.22 dBc/Hz. The ADPLL achieves a power efficiency of 9.2370 mW/GHz.
摘要 I
Abstract II
誌謝 IV
目錄 V
圖目錄 VII
表目錄 XI
第一章 緒論 1
1.1 動機 1
1.1.1 設計目標與規格 1
1.2 頻率合成器之架構介紹 2
1.2.1 直接類比式頻率合成器 3
1.2.2 直接數位式頻率合成器 3
1.2.3 間接頻率合成器 4
1.3 論文組織 5
第二章 鎖相迴路的基本概念 6
2.1 類比式鎖相迴路 6
2.1.1 相位頻率偵測器 7
2.1.2 充放電幫浦 10
2.1.3 迴路濾波器 11
2.1.4 電壓控制震盪器 12
2.1.5 除頻器 13
2.1.6 整體鎖相迴路分析 14
2.2 全數位式鎖相迴路 16
2.2.1 快速鎖定之全數位鎖相迴路文獻參考 17
2.2.2 寬幅調整之數位控制震盪器文獻參考 20
第三章 寬幅調整且快速鎖定全數位式鎖相迴路之分析 24
3.1 頻率捕捉模式 (Frequency Acquisition Mode) 25
3.1.1 假位法 (Regula Falsi) 25
3.1.2 與其他方法之比較 30
3.2 相位追蹤模式 (Phase Tracking Mode) 31
3.2.1 相位追蹤概念 32
3.2.2 穩定度分析 33
3.2.3 鎖相迴路線性模型 38
3.2.4 相位雜訊分析 40
第四章 寬幅調整且快速鎖定全數位式鎖相迴路之實現 46
4.1 全數位式鎖相迴路之架構 46
4.2 全數位式鎖相迴路之狀態機 48
4.3 頻率捕捉迴路 49
4.3.1 頻率捕捉架構 (FA Block) 49
4.4 相位追蹤迴路 51
4.4.1 相位偵測器 (Phase Detector) 51
4.4.2 數位迴路濾波器 (Digital Loop Filter) 52
4.4.3 數位控制振盪器 (Digitally Controlled
Oscillator) 54
4.4.3.1 數位控制震盪器佈局考量 60
4.4.4 預除器 (Prescaler) 61
4.4.5 計數器 (Counter) 63
4.5 實現方式 64
第五章 模擬結果 66
5.1 數位控制震盪器之模擬結果 66
5.2 鎖相迴路之模擬結果 74
5.2.1 NC-Verilog迴路模擬 74
5.2.2 SPICE迴路模擬 80
5.3 電路佈局圖 85
第六章 鎖相迴路晶片量測結果 87
6.1 可程式化邏輯閘陣列配合震盪器晶片量測 87
6.2 鎖相迴路晶片照 90
6.3 測試板之配置 91
6.4 數位控制振盪器之量測結果 92
6.4.1 轉換曲線 (Transfer Curve) 92
6.5 全數位式鎖相迴路之量測結果 94
6.5.1 鎖定速度表現 94
6.5.2 輸出頻率之抖動表現 (Jitter) 99
6.5.3 輸出頻率之相位雜訊 (Phase Noise) 103
6.5.4 功率消耗 109
6.6 表現總結 112
第七章 結論與未來展望 114
7.1 結論 114
7.2 未來展望 115
參考文獻 117

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