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研究生:劉仁傑
研究生(外文):Jen-Chieh Liu
論文名稱:全數位式鎖相迴路之設計與內建時脈抖動量測之應用
論文名稱(外文):Design of All Digital Phase-Locked Loop and Application in Built-in Jitter Measurement
指導教授:黃弘一鄭國興鄭國興引用關係
指導教授(外文):Hong-Yi HuangKuo-Hsing Cheng
學位類別:博士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:114
中文關鍵詞:低電壓操作內建時脈抖動量測電路全數位式鎖相迴路
外文關鍵詞:low supply voltageBuilt-in Jitter MeasurementAll Digital Phase-Locked Loop
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隨著綠能時脈系統的演進,具高速低功率之鎖相迴路(Phase-locked loop, PLL)與延遲迴路(Delay-locked loop, DLL)被提出來解決時脈的偏移問題。因此,低抖動量與高頻率精準度之時脈電路被用以提高可靠度與系統正確性。在低電壓操作應用中,其低功率的時脈產生器可以有效地延長電池的壽命。低電壓操作中,時脈分佈網域系統的時脈抖動會影響更顯著。所以時脈抖動量必須盡可能的降低與其抖動數值也必須小於時脈系統可以接受的範圍內。而且高頻晶片系統設計,採用內建式時脈量測電路用以量測時脈訊號的抖動量,可以有效的降低高頻測試之成本。
首先,本論文提出使用數位式電壓穩壓器以降低電壓雜訊與可達到高速具多相位功能之全數位式鎖相迴路(All digital phase-locked loops, ADPLLs)。其中,以數位式電壓穩壓器降低電壓雜訊影響之全數位式鎖相迴路。在數位式控制振盪器中,以一顆MOS元件擁有兩種解析度的數位電容器到達較高速頻率操作。當在電源上加入雜訊源後,其輸出訊號陡動可以降低至0.38% –TPLL / 1%–VDD。將雜訊加入整個全數位式鎖相迴路的電壓源後,其方均根抖動量(RMS jitter) 仍然可以小於 1%。另外,在數位式振盪器採用負迴授的電路架構之全數位式鎖相迴路,可以提高電路的操作頻率。在數位對時間轉換器中,採用多相位的取樣電路與時間放大器電路可以達到小面積與增加時間解析度的優點。因此,具數位式電壓穩壓器與多相位數位式振盪器擁有數位對時間轉換器功能可以有效操作於極低電壓之應用。
接著,本論文提出內建抖動測試電路(Built-in jitter measurements, BIJMs)量測時脈抖動並應用於高速傳輸介面與晶片系統。內建抖動測試電路採用提高時間解析度與自我校正的技巧。游標尺之環型振盪器(Vernier ring oscillator, VRO)與具多相位環形振盪器之取樣電路(Multi-phase sampler, MPS)可降低電路面積。採用時間放大電路的技巧可延伸抖動量測電路的解析度。在製程補償方面,調變時間放大器的增益與游標尺之環型振盪器或多相位取樣電路的解析度,亦可在製程變異下,達到高解析度功能。自我參考電路(Self-referenced circuit)使用自動校正電路並不需要額外提供一參考訊號。故在十億赫茲的操作頻率下,可以容易地實現於時脈系統中。
在本論文中所提出低電壓操作之全數位式鎖相迴路與內建抖動測試電路,可應用於時脈分佈網域系統。因此,在晶片系統中,全數位式鎖相迴路與內建抖動測試電路更具彈性於可重覆使用之矽智產設計。
With green energy-saving clocking systems, the high speed and low power consumption phase-locked loop (PLL) and delay-locked loop (DLL) are popular to solve the clock skew. The low jitter and high frequency accuracy of clock sources can improve the reliability and correctness of system. For low supply voltage application, the low power clock generators are adopted to extend the battery life. In clock distribution networks, the clock jitter may be large at low supply voltages. Thus, the clock jitter must be reduced and less than the jitter tolerance of clocking system. To measure the clock jitter, the jitter measurement circuits are useful to build in a system-on chip (SoC) and reduce the testing cost at high operational frequency clocking systems.
First, ultra low voltage all-digital phase-locked loops (ADPLLs) are proposed for the digital supply regulator to limit the digital controlled oscillator (DCO) supply noise effects and high speed DCO with multi-phase outputs. One adopts a digital supply regulator to reduce the noise supply effects. The DCO uses the two-step timing resolution of a digital controlled varactor to achieve the high operational frequency. By injecting the supply noise into the DCO, the ADPLL output jitter is limited to 0.38% –TPLL / 1% – VDD. When the supply noise is mixed into the ADPLL supply, the RMS jitter is less than 1%. The other employs a sub-feedback loop DCO scheme at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme to reduce the area and adopts a timing amplifier to extend the timing resolution of TDC. Therefore, the digital supply regulator and multi-phase DCO embedding a TDC are useful under the lower supply voltage applications.
Next, built-in jitter measurement circuits (BIJMs) are proposed to measure the clock jitter on high speed transceivers and SoC systems. The proposed BIJM circuits adopt a high timing resolution and self-calibration techniques. The vernier ring oscillator (VRO) and proposed multi-phase sampler (MPS) can reduce the area and the TA can extend the total timing resolution of BIJM. Using the calibration technique, the gain variation of TA and the timing resolution variation of VRO or MPS can be aligned to make sure timing resolution of BIJM. The self-referenced circuit with an auto-calibration technique can eliminate the process variations and create a reference clock being a sampled signal. BIJM circuits do not need an additional jitter-free reference signal using the self-referenced circuit. In the giga-hertz operational frequency, the proposed designs can be easy to build in clock source systems.
In the dissertation, we proposed the ultra low supply voltage ADPLLs and the built-in jitter measurement circuits in clock distribution networks. Thus, the ADPLLs and BIJM circuits are also suitable for reuse IPs in SoC systems.
Contents
摘要 i
Abstract iii
誌謝 vi
Contents vii
Figure Captions x
Table Captions xiv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Analysis and Design of BIJM for Clocking Systems 4
1.3 Thesis Organization 5
Chapter 2 The Basics of All Digital PLLs and Built-in Jitter Measurement Circuits 7
2.1 Phase-Locked Loop 7
2.2 Overview of All Digital PLLs 9
2.2.1 WIDE POWER SUPPLY RANGE ADPLL 10
2.2.2 PVT TOLERANT AND CALIBRATION-FREE ADPLLS 11
2.2.3 LC-TANK BASED DIGITAL PLL 13
2.2.4 ALL DIGITAL SPREAD-SPECTRUM PLL 14
2.2.5 SUMMARY 15
2.3 Built-in Jitter Measurement Circuits 16
2.3.1 VERNIER DELAY LINE BASED TDC 17
2.3.2 VERNIER RING OSCILLATOR BASED TDC 18
2.3.3 TDC WITH TIMING AMPLIFIER CIRCUITS 18
2.3.4 CYCLIC PULSE-SHRINKING TDC 19
2.3.5 CHARGE-PUMP PLL EMBEDDING A TDC 20
2.3.6 SUMMARY 20
Chapter 3 An Ultra Low Voltage All Digital PLL with a Digital Supply Regulator 23
3.1 Architecture of ADPLL with a DSR 23
3.1.1 DIGITAL SUPPLY REGULATOR WITH AN AUTO-CALIBRATION CIRCUIT 25
3.1.2 DIGITAL CONTROLLED OSCILLATOR 29
3.1.3 DOUBLE EDGE TRIGGER DIGITAL LOOP FILTER 32
3.1.4 PFD AND TDC 34
3.2 Stability and Noise Analysis of ADPLL 35
3.2.1 BEHAVIOR MODEL OF ADPLL 35
3.2.2 NOISE ANALYSIS OF ADPLL 37
3.3 Experiment Results 39
3.3.1 CONCEPT 39
3.3.2 MEASURED ENVIRONMENT SETUP 39
3.3.3 0.5 V AND 0.6 V ADPLL 40
3.3.4 SUPPLY VOLTAGE SENSITIVITY OF ADPLL 44
Chapter 4 A Multi-phase All Digital PLL Embedding a TDC 47
4.1 Architecture of Multi-phase ADPLL 47
4.1.1 ANALYSIS AND IMPLEMENTATION OF THE PROPOSED MULTI-PHASE DCO 48
4.1.2 MULTI-PHASE-BASED TDC WITH A TA 53
4.2 Stability of Multi-phase DPLL Using a MP-TDC 56
4.3 Experiment Results 57
4.3.1 CONCEPT 57
4.3.2 MEASURED RESULTS 57
Chapter 5 A BIJM Circuit with Calibration Techniques 63
5.1 Architecture of BIJM with Calibration Techniques 63
5.1.1 CALIBRATION MODE 64
5.1.2 JITTER MEASUREMENT MODE 65
5.1.3 VERNIER RING OSCILLATOR WITH A CALIBRATION TECHNIQUE 67
5.1.4 TIMING AMPLIFIER USING A PROGRAMMABLE TA GAIN 68
5.1.5 SELF-REFERENCED CIRCUIT 71
5.1.6 WRITE / READ COUNTER 72
5.1.7 TOTAL TIMING RESOLUTION AND JITTER HISTOGRAM 73
5.2 Measured error Analysis 77
5.3 Measured results 79
5.3.1 CONCEPT 79
5.3.2 CALIBRATION AND JITTER MEASUREMENT MODES 80
5.3.3 MEASURED ERROR 83
Chapter 6 A BIJM Circuit Using a Multi-phase Sampler 85
6.1 Architecture of BIJM with a MPS 85
6.1.1 PRINCIPLE OF THE BIJM SYSTEM 85
6.1.2 MULTI-PHASE OSCILLATOR 87
6.1.3 MULTI-PHASE SAMPLER 90
6.1.4 TA WITH A CALIBRATION CIRCUIT 92
6.1.5 WRITE / READ COUNTER 94
6.2 Measured error Analysis 94
6.3 Simulated results 96
6.3.1 CALIBRATION MODE 96
6.3.2 JITTER HISTOGRAM 98
6.4 Experiment Results 99
6.4.1 CONCEPT 99
6.4.2 MEASURED RESULTS 99
Chapter 7 Conclusions and Future Works 105
7.1 Conclusions 105
7.2 Future Works 107
References 108
Publication List 113
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