臺灣博碩士論文加值系統

本篇論文提出一個基於時脈閘控(clock-gating)技術，可節省動態功率(dynamic power)消耗的管線(pipeline)架構；此架構充分利用穿透管線(transparent pipeline)觀念，將管線內暫存器(register)在適當情況下動態地變成穿透狀態，以減少電路中訊號轉換所造成的動態功率消耗。

　　本文提出之管線架構以兩種電路為基礎，分別為連鎖管線(interlock pipeline)以及彈性電路(elastic circuit)，此兩種電路皆近似非同步電路之特性，使其在低功率(low power)方面有相當好的表現；連鎖管線本身的設計目的是以同步電路模擬非同步電路之特性，使具備非同步的優點，而非同步電路特性其中之一就是區域性(locality)，代表電路可在局部產生變化而不完全影響整體電路的運作，因此訊號轉換也只在局部發生，亦達成較少的動態功率消耗；而彈性電路在基本架構上也與連鎖管線之功能相近，兩者間的主要差異在於控制電路，除了在資料路徑上的控制電路不同外，連鎖管線中的有效訊號閂鎖器是由額外的控制電路來控制，以達成與資料同時暫停之功能，而彈性電路中的有效訊號閂鎖器則是透過時脈訊號直接控制，而為了補償遺失的有效訊號，則是經由進入管線中之暫停訊號來替補。

　　因此基於時脈閘控技術、穿透特性以及區域性的相輔相成下，實現兩個具備非同步特性且可節省動態功率消耗之同步管線架構，並比較分析這兩種架構。

This paper presents a pipeline structure based on clock-gating technique which can save dynamic power consumption. This structure fully uses transparent technique, and makes the registers of the intermediate stages into transparent mode dynamically to reduce dynamic power consumption of switching signal state.

The proposed structure based on two circuits, one is interlock pipeline and the other is elastic circuit. These two circuits are similar to asynchronous characteristics, and make it having good performance of low power. The main design purpose of interlock pipeline is simulating asynchronous circuit to have the advantages of asynchronous. One of asynchronous advantages is locality, it means the stages work locality without affecting whole circuit work. According to the foregoing, signal also switches locality and decrease the dynamic power consumption. Elastic circuit works similarly to interlock pipeline, the main difference between them is the control logic. There is one more control logic to control the valid latches in interlock pipeline, but in elastic circuit, there is no control logic in elastic circuit but using clock signal directly.

Finally, according to clock gating、transparent technique and locality, we implement two pipeline structures which can save dynamic power consumption and have the characteristic of asynchronous circuit, and compare these two structures at last of paper.

目錄
中文摘要 I
英文摘要 II
誌謝 III
目錄 IV
圖目錄 V
表目錄 VI
第一章 緒論 1
第一節 研究背景與動機 1
第二節 時脈閘控技術 2
第三節 穿透管線 3
第三章 架構基礎及提出方法實現 9
第一節 連鎖管線 9
第二節 基於連鎖管線之提出架構 12
第三節 彈性電路 14
第四節 基於彈性電路之提出架構 16
第四章 實驗結果 19
第一節 電路模擬結果 19
第二節 模擬結果分析 25
第五章 結論 27
參考文獻 28



圖目錄
圖1. 傳統時脈閘控管線 2
圖2. 穿透管線 3
圖3. 穿透管線各時脈週期運作圖 4
圖4. 傳統時脈閘控控制電路 8
圖5. 穿透級控制電路 8
圖6. 連鎖管線架構圖 9
圖7. 控制電路訊號相對應之名稱 10
圖8. 連鎖管線閂鎖器控制電路 11
圖9. 以連鎖管線為基礎提出之四級管線架構 12
圖10. 彈性電路架構圖 14
圖11. 以彈性電路為基礎提出之中間級管線架構 16
圖12. 資料閂鎖器控制電路 17
圖13. 單筆資料與連續多筆資料 21
圖14. 單筆資料及連續暫停訊號與間隔資料及單筆暫停訊號 23
圖15. 連續多筆資料、間隔資料及暫停訊號 24



表目錄
表1：4級傳統時脈閘控管線 6
表2：4級穿透管線 6
表3：資料控制電路真值表 18
表4：模擬波形圖訊號之對應位置 19
表5：模擬波形圖訊號之對應閂鎖器 20
表6：4級管線電路面積比較表 26
表7：8級管線電路面積比較表 26

參考文獻
[1]V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez, “Reducing Power in High-Performance Microprocessors,” in Proc. Design Automation Conference, 1998 , pp. 732–737.
[2]T. Mudge, “Power: A first-class architectural design constraint,” IEEE Trans. Computer, vol. 34, no. 4, pp. 52–58, April 2001.
[3]H. M. Jacobson, “Synchronous Pipeline With Normally Transparent Pipeline Stages,” United State Patent, US 7,076,682 B2.
[4]A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-Power Digital CMOS Design,” IEEE Journal of Solid State Circuits, pp. 473-484, April 1992.
[5]A. Correale, JR., “Overview of the Power Minimization Techniques
Employed in the IBM PowerPC 4xx Embedded Controllers,” in Proc. International Symposium on Low Power Electronics and Design (ISLPED), 1995, pp. 75–80.
[6]M. K. Gowan, L. L. Biro, and D. B. Jackson, “Power Considerations in the Design of the Alpha 21264 Microprocessor,” in Proc. Design Automation Conference, 1998, pp. 726–731.
[7]H. Shimada, H. Ando, and T. Shimada, “Pipeline Stage Unification: A Low-Energy Consumption Technique for Future Mobile Processors,” in Proc. the International Symposium on Low Power Electronics and Design, 2003, pp. 326–329.
[8]H. M. Jacobson, “Improved Cock-Gating through Transparent Pipelining,” in Proc. the International Symposium on Low Power Electronics and Design, 2004, pp. 26–31.
[9]J. H. Choi, B. G. Kim, A. Dasgupta, and K. Roy, “Improved Clock-Gating Control Scheme for Transparent Pipeline,” in Proc. the Asia and South Pacific Design Automation Conference, 2010, pp. 401-406.
[10]H. M. Jacobson, P. N. Kudva, P. Bose, P. W. Cook, and S. E. Schuster, “Synchronous Interlocked Pipelines,” in Proc. Eighth International Symposium on Asynchronous Circuit and Systems, 2002, pp. 3-12.
[11]I. E. Sutherland, “Micropipelines,” in Proc. Communications of the ACM, vol 32, no. 6, 1989, pp. 720-738.
[12]J. Carmona, J. Cortadella, M. Kishinevsky, and A. Taubin, “Elastic Circuits,” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1437-1455, Oct 2009.
[13]J. Carmona, M. Galceran-Oms, and M. Kishinevsky, “Elastic Systems,” IEEE Formal Methods and Models for Codesign (MEMOCODE), vol. 28, no. 10, pp. 1437-1455, Oct 2009.
[14]L. P. Carloni, K. L. McMillan, A. Saldanha, and A. L. Sagiovanni- Vincentelli, “A Methodology for Correct-by-Construction Latency Insensitive Design,” in Proc. ICCAD, 1999, pp. 309–315.