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研究生:陳山榮
研究生(外文):Shan-Rong Chen
論文名稱:低電壓之低功耗雙頻帶/寬頻帶低雜訊放大器設計
論文名稱(外文):The Design of Low Power Dual-band / Wideband Low Noise Amplifier with Low Voltage
指導教授:翁若敏
指導教授(外文):Ro-Min Weng
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
論文頁數:114
中文關鍵詞:低雜訊放大器帶拒濾波器帶通濾波器基級順向偏壓
外文關鍵詞:Low Noise AmplifierNotch FilterBandpass FilterForward Body Bias
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本論文完成了可應用在生醫領域的可攜式設備上之電路設計。論文內容裡包含了兩個低雜訊放大器晶片設計,主要特性為可達到低功耗、低雜訊、頻率選擇、頻寬延展以及改善整體增益的平坦度。
第一顆為應用於0.9與2.45GHz雙頻帶之低雜訊放大器晶片設計。主要是輸入端採用帶拒濾波器的架構來達到輸入匹配與最大功率轉移。再利用折疊式的電路架構將所需的供應電壓降低,其中有一電晶體使用基級順向偏壓的技巧以確保可以低電壓操作,藉此達到整體功率消耗的下降。第二顆為0.9~3.5GHz之寬頻帶低雜訊放大器晶片設計,此電路在於輸入匹配採用了帶通濾波器架構,利用一個置放在輸入訊號端與整體電路的第一顆電晶體間的電感來達到頻寬延展。接下來利用互補式電晶體架構作為提升增益與降低雜訊的關鍵,其中也利用基級順向偏壓的技巧來確保與調整互補式架構。在同樣擁有整體電路消耗功率低的特性下,可達到增益放大的效果。
以上兩顆晶片都是利用安捷倫公司的電路模擬軟體Advanced Design System(ADS)完成模擬與設計;思源科技公司的電路佈局軟體Laker完成電路佈局,並採用國家晶片中心所提供的TSMC 0.18-um 1P6M CMOS製程模擬與製作,晶片採用on-wafer方式進行量測。
第一顆雙頻帶低雜訊放大器晶片的模擬特性如下:操作電壓為0.6(V),消耗功率為4.76(mW),於0.9GHz與2.45GHz時輸入反射損耗(S11)分別為-13.5(dB)與-11.4(dB),輸出反射損耗(S22)分別為-13.7(dB)與-10(dB),增益(S21)分別為14.7(dB)10.1(dB),隔離度(S12)分別為-55.1(dB)與-47.3(dB),-1分貝增益壓縮點(P-1dB)分別為-17(dBm)與-15(dBm),輸入三階截斷點(IIP3)分別為-24(dBm)與-16(dBm),雜訊指數(NF)分別為4.5(dB)與3.5(dB),晶片面積0.9 × 1.14mm2。
第二顆寬頻帶低雜訊放大器晶片的模擬特性如下:操作電壓為1(V),消耗功率為9.64(mW),輸入反射損耗(S11)皆小於-10.55 (dB),輸出反射損耗(S22)皆小於-10.23 (dB),增益(S21)皆大於10.46 (dB),隔離度(S12)皆小於-72.02 (dB),於2.4GHz 時,-1分貝增益壓縮點(P-1dB)為-8.35(dBm),輸入三階截斷點(IIP3)為-8(dBm),雜訊指數(NF)皆小於3.3(dB),晶片面積0.98 × 0.91mm2。
The CMOS radio frequency (RF) circuits have been applied to portable biomedical equipment are presented in this thesis. There are two low noise amplifiers(LNA) design which are low power dissipation, low noise, frequency selection, bandwidth extension, and gain flatness improvement.
The first chip is a concurrent dual-band LNA(DBLNA). A band reject input matching network is used to achieve maximum power transfer. The operating frequencies are 0.9GHz and 2.45GHz. A folded circuit topology is used to reduce supply voltage. A forward body bias (FBB) technology is employed to ensure low supply voltage operation and to reduce total power dissipation.
The second chip is a wideband low noise amplifier (WLNA). The operating frequency is 0.9~3.5GHz. A band-pass input matching network is used. An inductor is placed between the input signal port and the first transistor to extend desired bandwidth. A complementary topology is used to boost gain and reduces noise performance. A FBB technique is used to ensure and to adjust gain boosting of complementary topology with low power consumption.
The proposed LNA chips are simulated by using Agilent circuit simulation software (Advanced Design System). The chips are layout by using SpringSoft circuit layout software (Laker). TSMC 0.18-um CMOS standard process is chosen to fabricate through CIC. The measurement of the front-end chip is done by using an on-wafer method.
The simulated results of the first chip (DBLNA) are as follow:
The supply voltage is 0.6(V). The power consumption is 4.76(mW). The input return loss (S11) are -13.5(dB) for 0.9GHz and -11.4(dB) for 2.45GHz. The output return loss (S22) are -13.7(dB) for 0.9GHz and -10(dB) for 2.45GHz.The forward transmission coefficient (S21) are 14.7(dB) for 0.9GHz and 10.1(dB) for 2.45GHz. The reverse transmission coefficient (S12) are -55.1(dB) for 0.9GHz and -47.3(dB) for 2.45GHz. The -1dB gain compression point (P-1dB) are -17(dBm) for 0.9GHz and -15(dBm) for 2.45GHz. The input third order intercept point(IIP3) are -24(dBm) for 0.9GHz and -16(dBm) for 2.45GHz. The noise figure are 4.5(dB) for 0.9GHz and 3.5(dB) for 2.45GHz.The chip area is 0.9 × 1.14mm2.
The simulated results of the second chip (WLNA) are as follow:
The DC supply voltage is 1V. The power consumption is 9.64mW. The input return loss (S11) is less than -10.55dBin the pass band. The output return loss (S22) is less than -10.23dB. The forward transmission coefficient (S21) is larger than 10.46dB. The reverse transmission coefficient (S12) is less than -72.02dB. The -1dB gain compression point (P-1dB) is -8.35dBm at 2.4GHz. The input third order intercept point(IIP3) is -8dBm at 2.4GHz. The noise figure is less than 3.3dB. The chip area is 0.98×0.91mm2.
誌謝 I
中文摘要 IV
Abstract VI
Contents VIII
List of Figures X
List of Tables XIV
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Receiver Architecture 2
1.3 Receiver Fundamentals 3
1.3.1 Noise Figure 3
1.3.2 Linearity 5
1.4 Architecture of the Thesis 7
Chapter 2 CMOS Low Noise Amplifier 9
2.1 LNA Topology 9
2.1.1 Cascode LNA with Source Degeneration Inductor 9
2.1.2 LNA with Filter Topology 12
2.1.3 LNA in Complementary Structure 18
2.2 Low Power Design 21
2.2.1 Low Supply Voltage 21
2.2.2 Current Reuse 22
2.2.3 Forward Body Bias 24
Chapter 3 Proposed LNA and Measured Results 27
3.1 A Concurrent Dual-band LNA in Ultra Low Power 27
3.1.1 Design Guidelines 27
3.1.2 Impedance Matching with Notch Filter 31
3.1.3 Low Supply Voltage Design 37
3.1.4 Forward Body Bias Design 39
3.1.5 Output Matching and Gain Adjustment 40
3.1.6 Simulated and Measured Results 43
3.2 A Low Power Low Noise Amplifier with Gain Flatness and Noise Optimization 58
3.2.1 Design Guidelines 58
3.2.2 Impedance Matching with Band-pass Filter 63
3.2.3 Design of Extending Bandwidth and Gain Flatness Enhancement 67
3.2.4 Forward Body Bias Design 69
3.2.5 Output Matching and Gain Adjustment 70
3.2.6 Simulated and Measured Results 72
3.2.7 Summary and Discussion 86
Chapter 4 Conclusion and Future Work 89
4.1 Conclusion 89
4.1.1 Dual-band LNA 89
4.1.2 Wideband LNA 89
4.2 Future Work 90
Bibliography 95
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