臺灣博碩士論文加值系統

本論文提出一種適用於飛加器頻率合成器的加法器架構並使用FPGA完成驗證，此加法器的概念為打亂加法器的週期，從而降低分數突刺。而我們也使用FPGA來實作不同類型的飛加器頻率合成器。
飛加器頻率合成器所使用的單元有多工器、加法器、數位至電壓轉換器、電壓控制延遲線、除頻器、數位內插器、控制單元等、使用連續逼近式暫存器電路來做為鎖定的演算法，也就是二元搜尋法，以達到快速鎖定的目的，電壓控制延遲線輸出八個相位再配合數位內插器，能輸出十六個相位供飛加器使用，在晶片設計上以多相位數位內插器來減少面積。
晶片使用台積電0.18μm製程實現，佈局電路核心面積為320.42×337.76μm2，採用28 Pin之ESD保護電路，整體晶片面積為937×937μm2。飛加器頻率合成器輸出頻率範圍為60MHz~110 MHz，當量測飛加器頻率合成器輸出頻率為62.28MHz時，峰對峰值(Peak-to-Peak) jitter為282.41ps，(均方根值)RMS jitter為47.07ps。

This thesis presents the adder architecture for the flying-adder frequency synthesizer and the using the FPGA to complete the verification. The basic concept of this adder is to disrupt the cycle of the adder, thereby it reduces fractional spur. We also use the FPGA to implement the different types of flying-adder frequency synthesizer.
Flying-adder frequency synthesizer’s basic unit contains multiplexer, adder, digital-to-voltage converter, delay-locked loop, divider, digital interpolator and control unit. The SAR circuit uses to do lock algorithm, which is the binary search method, to achieve the purpose of fast locking. DLL output eight phases are interpolated with the digital interpolators. The DLL can output the 16 phases for the flying-adder. Multiphase digital Interpolator reduces the chip area.
The chip has been implemented in TSMC 0.18μm. The core area of the chip is 320.42×337.76μm2 and the total area is 937×937μm2. Flying-adder frequency synthesizer output frequency ranges from 60MHz ~ 110 MHz. The peak-to-peak jitter is 282.41ps and RMS jitter is 47.07ps when flying-adder frequency synthesizer’s output frequency is 62.28MHz.

摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VIII
表目錄 XIV
第一章 緒論 1
1.1文獻探討 1
1.2研究動機與目的 3
1.3論文架構 4
第二章 飛加器使用Verilog HDL及FPGA實現 5
2.1 Verilog HDL簡介 5
2.2 FPGA簡介 6
2.2.1 FPGA架構 9
2.3 飛加器頻率合成器簡介 11
2.4 單路徑飛加器頻率合成器架構介紹 12
2.4.1 單路徑飛加器頻率合成器(整數合成) 13
2.4.2 單路徑飛加器頻率合成器(小數合成) 17
2.5雙路徑飛加器頻率合成器架構介紹 19
2.5.1 雙路徑飛加器頻率合成器(整數合成) 20
2.5.2 雙路徑飛加器頻率合成器(小數合成) 25
2.6具有控制相位之飛加器頻率合成器架構介紹 27
2.6.1 具有控制相位之飛加器頻率合成器(整數合成) 28
2.6.2 具有控制相位之飛加器頻率合成器(小數合成) 30
2.7飛加器公式推導及比較 32
2.7.1飛加器合成頻率公式推導 32
2.7.2飛加器合成頻率抖動(Jitter)分析 33
2.7.1飛加器頻率合成器特點 35
2.8 FPGA實現 36
2.8.1 FPGA模擬單路徑飛加器頻率合成器 37
2.8.2 FPGA模擬雙路徑飛加器頻率合成器 39
2.8.3 FPGA模擬具相位控制飛加器頻率合成器 43
2.8.4 加法器 45
第三章 晶片設計及量測 50
3.1 延遲鎖定迴路簡介 50
3.2 飛加器架構簡介 51
3.3 系統架構與設計原理 52
3.4 電路設計原理與模擬 55
3.4.1相位偵測器(Phase Detector) 55
3.4.2連續逼近暫存器(Successive Approximation Register) 58
3.4.3數位至電壓轉器(Digital-to-Voltage Converter) 61
3.4.4電壓控制延遲線(Voltage Controlled Delay Line) 65
3.4.5多相位數位內插器(Multiphase Digital Interpolator) 67
3.4.6飛加器頻率合成器(Flying-Adder Frequncy Synthesizer) 70
3.5 電路佈局與後模擬 75
3.6 全系統模擬 80
3.6.1全系統模擬之前模擬 80
3.6.2全系統模擬之後模擬 84
3.7 晶片量測 87
第四章 多相位校準技術 94
4.1多相位校準技術簡介 94
4.1.1連續循序相位調整校準 94
4.1.2遞迴相位調整校準技術 95
4.1.2改良型校準技術 97
4.2改良型校準電路架構 99
4.3改良型校準電路設計 100
4.3.1延遲線(Delay Line) 100
4.3.2內插器(Interpolator) 101
4.3.3上下數計數器(Up/Down Counter) 102
4.4電路佈局及後模擬 103
4.4.1延遲線佈局 103
4.4.2內插器佈局 104
4.4.3上下數計數器佈局 105
4.4.3全系統佈局 106
4.5 全系統模擬 107
第五章 結論與未來研究方向 111
5.1結論 111
5.2未來研究方向 112
參考文獻 113
附錄 116

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