誤碼率（BER）是任何數位通訊系統的性能的基本指標之一。傳統上，BER的評估使用蒙特卡洛模擬，這是非常耗費時間。在本論文中，我們實作了一個低成本的誤碼率測試架構。該架構結合了BERT和一個 AWGN訊號產生器實現在FPGA上。此外，基於 FPGA的解決方案，使得它很容易與待測物連接，適合用於系統發展時的測試。

The Bit error rate (BER) of any digital communication system is performance of the basic indicators. Traditionally, BER is assessed using Monte Carlo simulation, which is very time consuming. In this thesis, we implemented a low-cost error rate test structure. The structure combines a BERT and AWGN signal generator implemented in the FPGA. The FPGA-based solution can be used to be an interface with the developing system for testing.

中文摘要........................................... I
英文摘要........................................... II
目　　錄........................................... III
表 目 錄........................................... V
圖 目 錄........................................... V
第1章 緒論 1
1.1 研究動機.................................. 1
1.2 論文大綱.................................. 2
第2章 相關背景 3
2.1 誤碼率的簡介............................... 3
2.1.1 影響誤碼率的因素...................,....... 4
2.1.2 誤碼率和訊號雜訊比......................... 7
2.1.3 調變傳輸的誤碼率性能....................... 7
2.2 誤碼率測試儀............................... 10
2.2.1 偽隨機位元序列(PRBS)....................... 10
2.2.2 AWGN通道模型.............................. 11
2.3 誤碼率測試的計劃............................ 12
第3章 研究方法 14
3.1 誤碼率測試................................. 14
3.1.1 串行BERT設計............................... 15
3.1.2 並行BERT架構............................... 16
3.2 AWGN通道產生方法........................... 19
3.2.1 CLT方法................................... 19
3.2.2 Box-Muller方法........................... 20
3.2.3 混合方法.................................. 21
3.2.4 極化方法.................................. 22
3.3 極化方法的實作.............................. 23
3.3.1 隨機變量的生成............................. 23
3.3.2 一個高斯亂數產生器......................... 24
3.3.2.1 生成V1和S................................. 25
3.3.2.2 先進先出實施............................... 25
3.3.2.3 生成W..................................... 28
3.3.2.4 生成輸出.................................. 29
3.3.3 實現兩個高斯亂數產生器...................... 29
第4章 實驗結果 31
4.1 BERT設計架構............................... 31
4.1.1 BERT核心架構............................... 32
4.1.2 AWGN核心架構............................... 33
4.1.3 縮放係數與比對&輸出設置...................... 34
4.2 實驗結果.................................... 35
4.3 並行BERT選擇................................ 40
第5章 結論 42
參考文獻 ........................................... 43

表目錄
表4.1 誤碼率測量的結果比較......................... 38

圖目錄
圖1.1 數位通訊系統的架構圖......................... 2
圖2.1 數位通訊系統的基本要素....................... 5
圖2.2 PSK訊號符元錯誤概率.......................... 9
圖2.3 PRBS碼生成電路.............................. 11
圖2.4 AWGN通訊通道模型............................ 12
圖2.5 BERT架構圖.................................. 13
圖3.1 串行BERT架構................................ 15
圖3.2 並行BERT的架構.............................. 17
圖3.3 子模塊電路的並行BERT......................... 18
圖3.4 混合方法的架構圖............................. 21
圖3.5 單一AWGN產生器的架構圖....................... 24
圖3.6 同步FIFO的架構.............................. 26
圖3.7 繪製函數w(S)................................ 28
圖3.8 兩個AWGN產生器的架構圖....................... 30
圖4.1 BERT設計架構................................ 31
圖4.2 除2誤碼率測量的FPGA模擬圖..................... 36
圖4.3 除3誤碼率測量的FPGA模擬圖..................... 36
圖4.4 除4誤碼率測量的FPGA模擬圖..................... 37
圖4.5 除5誤碼率測量的FPGA模擬圖..................... 37
圖4.6 除6誤碼率測量的FPGA模擬圖..................... 38
圖4.7 測量誤碼率與理論誤碼率........................ 39
圖4.8 FPGA的LFSR序列.............................. 41

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