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研究生:周家慶
論文名稱:磷化銦/砷化銦鎵雙異質接面系列雙極性電晶體之研究
論文名稱(外文):Investigation of InP/InGaAs Series of Double Heterojunction Bipolar Transistors
指導教授:蔡榮輝蔡榮輝引用關係黃嘉宏黃嘉宏引用關係
學位類別:碩士
校院名稱:國立高雄師範大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
中文關鍵詞:磷化銦/砷化銦鎵雙異質接面雙極性電晶體磷砷化銦鎵補償電壓崩潰特性
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本論文中主要探討三種磷化銦/砷化銦鎵(InP/InGaAs)雙異質接面雙極性電晶體(DHBTs)和單異質接面雙極性電晶體(SHBT)之特性比較,以及討論在基-集極間加入不同材料和不同厚度間隙層之變化。該結構分別為:
(1)磷化銦/砷化銦鎵單異質接面雙極性電晶體(元件A)。
(2)傳統磷化銦/砷化銦鎵雙異質接面雙極性電晶體(元件B)。
(3)磷化銦/砷化銦鎵在基-集極間加入100埃及300埃未摻雜砷化銦鎵間隙層異質雙極性電晶體(元件C和D)。
(4)磷化銦/砷化銦鎵在基-集極間加入100埃及300埃未摻雜磷砷化銦鎵間隙層異質雙極性電晶體(元件E和F)。
我們透過理論模擬分析,由能帶圖可清楚的發現,傳統雙異質結構較單異質結構在基-集極間產生位障尖峰(potential spike),將會阻擋來自基極傳輸至集極的電子,使大部分的電子侷限在磷化銦/砷化銦鎵基-集極異質接面,使基極復合電流大增,進而降低電流增益,故電流增益遠低於單異質結構,模擬結果指出磷化銦/砷化銦鎵單異質結構元件(元件A)最大電流增益為344.8;集-射極補償電壓為68 mV。集極電流的理想因子接近1,表示電子傳輸經過基-射極接面是由擴散機制所主導,低電流區域基極電流的理想因子為1.49。而傳統磷化銦/砷化銦鎵雙異質結構元件(元件B)的最大電流增益為5.29;集-射極補償電壓為7.7 mV。集極電流的理想因子(nc)幾乎等於1,表示電子傳輸經過基-射極接面是由擴散機制所主導。低電流區域基極電流的理想因子為1.73,有大的復合。在崩潰特性方面,當我們定義電流為-1x10-5 A時,基-集極的反向電壓分別為-0.68 V和-19.61 V,可以由此看出傳統DHBT崩潰特性比SHBT更好,原因是DHBT在集極使用大能隙InP材料會使元件承受崩潰電壓愈高。另一方面,在雙異質結構基-集極之間加入一層未摻雜100埃或300埃砷化銦鎵的間隙層,同樣透過理論模擬分析,其能帶圖可以清楚看出此結構可以有效拉低基-集極位障尖峰,該元件的最大電流增益分別為90.6和191.1,這表示在基極與集極間加入一層未摻雜的砷化銦鎵層可以有效減少電子傳輸中受到位障的阻擋,獲得較大的電流增益。在基-集極之間加入一層未摻雜100埃 (元件C) 和300埃 (元件D) 砷化銦鎵間隙層的DHBT其集-射極補償電壓皆為11.5 mV;集極電流的理想因子(nc)皆近乎為1,而在低電流區域基極電流的理想因子分別為1.34和1.58,元件D在基-集極接面之間電子容易被導電帶不連續所形成的三角井捕捉,因此復合電流也較多。在崩潰特性方面,元件C和元件D的基-集極反向電壓分別為-19.4 V和-18.5 V,由此可見加入砷化銦鎵間隙層300埃比加入100埃的崩潰電壓小,原因是基-集接面處電場最大,略厚的砷化銦鎵小能隙的間隙層會使電子電洞對撞擊機率增加、崩潰電壓愈小。
另一方面,相較於前面的結構,磷化銦/砷化銦鎵雙異質接面電晶體在基-集極之間加入一層未摻雜100埃(元件E)或300埃(元件F)磷砷化銦鎵的間隙層。從能帶圖分析可看出,由於加入的磷砷化銦鎵能隙介於磷化銦和砷化銦鎵之間,可使得原來磷化銦和砷化銦鎵能隙差所造成的位障尖峰消除分成兩個較低的小尖峰,該元件的最大電流增益分別為21.5和123.2,顯示在基極與集極間加入一層未摻雜300埃的磷砷化銦鎵層可以有效減少電子傳輸中受到高位的阻擋,獲得的增益比加入300埃的砷化銦鎵層還要大。元件E和元件F的集-射極補償電壓皆為6.6 mV,集極電流的理想因子(nc)亦近乎為1,元件E和元件F在低電流區域基極電流的理想因子分別為1.49和1.73,元件F在基-集極接面之間電子容易被導電帶不連續所形成的三角井所捕捉,而且磷砷化銦鎵能隙比砷化銦鎵大,因此復合電流也相對較大。在崩潰特性方面,元件E和元件F的基-集極反向電壓分別為-19.73 V和-20.34 V,由於In0.72Ga0.28As0.61P0.39 的能隙大於In0.53Ga0.47As,而且元件F的厚度比元件E更厚,所以元件F的反向電壓愈大。
結果顯示磷化銦/砷化銦鎵雙異質接面電晶體在基-集極間加入適當的間隙層厚度,可以有效地降低位障尖峰,增加電流增益,並保持低的補償電壓,且提升高頻特性,適用於功率電路上。

CONTENTS
Abstract (Chinese) i
Abstract (English) iv
Table Lists
Figure Captions
Chapter 1. Introduction……………………………………………………………...1
Chapter 2. Comparison of InP/InGaAs/InP Double and InP/InGaAs Single Heterojunction Bipolar Transistors
2-1 Introduction…………………………………………………………………6
2-2 Device Structures…………………………………………………………...7
2-3 Simulated Results and Discussion…………………………………………..8
2-4 Conclusion…………………………………………………………………12
Chapter 3. InP/InGaAs/InP Double Heterojunction Bipolar Transistors with InGaAs Spacer at Base-Collector Junction
3-1 Introduction………………………………………………………………..13
3-2 Device Structures….…………………………………………...………….14
3-3 Simulated Results and Discussion…………………………………………15
3-4 Conclusion…………………………………………………………………17
Chapter 4. InP/InGaAs Double Heterojunction Bipolar Transistors with
InGaAsP Spacer at Base-Collector Junction
4-1 Overview…………………………………………………………………..19
4-2 Device Structures………………………………………………………….19
4-3 Comparison and Discussion………………………………….……………20
4-4 Conclusion…………………………………………………………………23
Chapter 5. Conclusions and Prospects
5-1 Conclusion…………………………………………………………………25
5-2 Prospects and Future Work………………………………………...………26
References
Tables
Figures







Table Lists
Table 1-1 Physical parameters of the simulated structures.
Table 2-1 Layer structure of the InP/InGaAs heterojunction bipolar transistor.
Table 2-2 Layer structure of the conventional InP/InGaAs double heterojunction bipolar transistor.
Table 2-3 Summary of the simulated performance of the devices A and B.
Table 3-1 Layer structure of the InP/InGaAs heterojunction bipolar transistors with different spacer thickness at base-collector junction.
Table 3-2 Summary of the simulated performance of the devices C and D.
Table 4-1 Layer structure of the InP/InGaAs/InGaAsP heterojunction bipolar transistors with different InGaAsP thickness.
Table 4-2 Summary of the simulated performance of the devices E and F.








Figure captions
Figure 2-1 (a) Schematic cross section of the InP/InGaAs single heterojunction bipolar transistor.
(b) Schematic cross section of the traditional InP/InGaAs double heterojunction bipolar transistor.
Figure 2-2 (a) Simulated energy band diagram of the InP/InGaAs single heterojunction bipolar transistor at equilibrium and VBC = -2 V.
(b) Simulated energy band diagram of the traditional InP/InGaAs double heterojunction bipolar transistor at equilibrium and VBC = -2 V.
Figure 2-3 (a) Comparison of electron concentrations in the device A and B.
(b) Comparison of hole concentrations in the device A and B.
Figure 2-4 (a) Simulated Gummel plots at VBC = 0 of the InP/InGaAs single heterojunction bipolar transistor.
(b) Simulated Gummel plots at VBC = 0 of the conventional InP/InGaAs double heterojunction bipolar transistor.
Figure 2-5 (a) Simulated turn-on voltages at B-E and B-C junctions of the InP/InGaAs SHBT.
(b) Simulated turn-on voltages at B-E and B-C junctions of the traditional InP/InGaAs DHBT.
Figure 2-6 (a) Simulated Base-collector (B-C) inverse voltage at the base current level of -10 μA of the InP/InGaAs SHBT.
(b) Simulated Base-collector (B-C) inverse voltage at the base current level of -10 μA of the InP/InGaAs DHBT.
Figure 2-7 (a) Common-emitter I-V characteristics of the InP/InGaAs single heterojunction bipolar transistor.
(b) Common-emitter I-V characteristics of the conventional InP/InGaAs double heterojunction bipolar transistor.
Figure 2-8 (a) Microwave performance of the InP/InGaAs single heterojunction bipolar transistor.
(b) Microwave performance of the conventional InP/InGaAs double heterojunction bipolar transistor.
Figure 3-1 (a) Schematic cross section of the InP/InGaAs double heterojunction bipolar transistor with a 100 Å undoped InGaAs spacer layer at B-C junction.
(b) Schematic cross section of the InP/InGaAs double heterojunction bipolar transistor with a 300 Å undoped InGaAs spacer layer at B-C junction.
Figure 3-2 (a) Simulated energy band diagram of the InP/InGaAs double HBT with a 100Å undoped InGaAs spacer layer between B-C junction at equilibrium and VBC = -2 V.
(b) Simulated energy band diagram of the InP/InGaAs double HBT with a 300Å undoped InGaAs spacer layer between B-C junction at equilibrium and VBC = -2 V.
Figure 3-3 (a) Comparison of electron concentrations in the device C and D.
(b) Comparison of hole concentrations in the device C and D.
Figure 3-4 (a) Simulated Gummel plots at VBC = 0 of the InP/InGaAs double heterojunction bipolar transistor with a 100Å undoped InGaAs spacer layer at B-C junction.
(b) Simulated Gummel plots at VBC = 0 of the InP/InGaAs double heterojunction bipolar transistor with a 300Å undoped InGaAs spacer layer at B-C junction.
Figure 3-5 (a) Simulated turn-on voltages at B-E and B-C junctions of the InP/InGaAs DHBT with a 100Å undoped InGaAs spacer layer at B-C junction.
(b) Simulated turn-on voltages at B-E and B-C junctions of the InP/InGaAs DHBT with a 300Å undoped InGaAs spacer layer at B-C junction.
Figure 3-6 (a) Simulated Base-collector (B-C) inverse voltage at the base current level of -10 μA of the InP/InGaAs DHBT with a 100Å undoped InGaAs spacer layer between B-C junction.
(b) Simulated Base-collector (B-C) inverse voltage at the base current level of -10 μA of the InP/InGaAs DHBT with a 300Å undoped InGaAs spacer layer between B-C junction.
Figure 3-7 (a) Common-emitter I-V characteristics of the InP/InGaAs DHBT with a 100Å undoped InGaAs spacer layer at B-C junction.
(b) Common-emitter I-V characteristics of the InP/InGaAs DHBT with a 300Å undoped InGaAs spacer layer at B-C junction.
Figure 3-8 (a) Microwave performance of the InP/InGaAs double heterojunction bipolar transistor with a 100Å undoped InGaAs spacer layer at B-C junction.
(b) Microwave performance of the InP/InGaAs double heterojunction bipolar transistor with a 300Å undoped InGaAs spacer layer at B-C junction.
Figure 4-1 (a) Schematic cross section of the InP/InGaAs double heterojunction
bipolar transistor with a 100 Å undoped InGaAsP spacer layer at B-C junction.
(b) Schematic cross section of the InP/InGaAs double heterojunction
bipolar transistor with a 300 Å undoped InGaAsP spacer layer at B-C junction.
Figure 4-2 (a) Simulated energy band diagram of the InP/InGaAs double heterojunction bipolar transistor with a 100Å undoped InGaAsP spacer layer between B-C junction at equilibrium and VBC = -2 V.
(b) Simulated energy band diagram of the InP/InGaAs double heterojunction bipolar transistor with a 300Å undoped InGaAsP spacer layer between B-C junction at equilibrium and VBC = -2 V.
Figure 4-3 (a) Comparison of electron concentrations in the device E and F.
(b) Comparison of hole concentrations in the device E and F.
Figure 4-4 (a) Simulated Gummel plots at VBC = 0 of the InP/InGaAs double heterojunction bipolar transistor with a 100Å undoped InGaAsP spacer layer at B-C junction.
(b) Simulated Gummel plots at VBC = 0 of the InP/InGaAs double heterojunction bipolar transistor with a 300Å undoped InGaAsP spacer layer at B-C junction.
Figure 4-5 (a) Simulated turn-on voltages at B-E and B-C junctions of the InP/InGaAs DHBT with a 100Å undoped InGaAsP spacer layer at B-C junction.
(b) Simulated turn-on voltages at B-E and B-C junctions of the InP/InGaAs DHBT with a 300Å undoped InGaAsP spacer layer at B-C junction.
Figure 4-6 (a) Simulated Base-collector (B-C) inverse voltage at the base current level of -10 μA of the InP/InGaAs DHBT with a 100Å undoped InGaAsP spacer layer between B-C junction.
(b) Simulated Base-collector (B-C) inverse voltage at the base current level of -10 μA of the InP/InGaAs DHBT with a 300Å undoped InGaAsP spacer layer between B-C junction.
Figure 4-7 (a) Common-emitter I-V characteristics of the InP/InGaAs DHBT with a 100Å undoped InGaAsP spacer layer at B-C junction.
(b) Common-emitter I-V characteristics of the InP/InGaAs DHBT with a 300Å undoped InGaAsP spacer layer at B-C junction.
Figure 4-8 (a) Microwave performance of the InP/InGaAs double heterojunction bipolar transistor with a 100Å undoped InGaAsP spacer layer at B-C junction.
(b) Microwave performance of the InP/InGaAs double heterojunction bipolar transistor with a 300Å undoped InGaAsP spacer layer at B-C junction.
[1] H. Kroemer, “Theory of a wide-gap emitter for transistors,” Proceedings of the Institute of Radio Engineers, vol. 45, no. 11, pp. 1535-1537, 1957.
[2] D. L. Miller and P. M. Asbeck, “Be redistribution during growth of GaAs and AlGaAs by molecular beam epitaxy,” J. Appl. Phys., no. 6, vol. 57, pp. 1816-1822, 1985.
[3] T. Won, S. Iyer, S. Agarwala, and H. Morkoc, “Collector offset voltage of heterojunction bipolar transistors grown by molecular beam epitaxy,” IEEE Electron Device Lett., vol. 10, no. 6, pp. 274-276, 1989.
[4] J. Y. Chen, D. F. Guo, S. Y. Cheng, K. M. Lee, C. Y. Chen, H. M. Chuang, S. Y. Fu, and W. C. Liu, “A new InP-InGaAs HBT with a superlattice-collector structure,” IEEE Electron Device Lett., vol. 57, no. 5, pp. 1816-1822, 2004.
[5] K. Ishii, H. Nosaka, M. Ida, K. Kurishima, M. Hirata, T. Enoki, and T. Shibata, “High-bit-rate low-power decision circuit using InP/InGaAs HBT technology,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1583-1588, 2005.
[6] S. Datta, S. Shen, K. P. Roenker, M.M. Cahay, and W. E. Stanchina, “Simulation and design of InAlAs/InGaAs pnp heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 45, no. 8, pp. 1634-1643, 1998.
[7] M. M. Jahan and A. F. M. Anwar, “Junction temperature dependence of high-frequency noise in heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 16, no. 12, pp. 551-553, 1995.
[8] U. Eriksson, P. Evaldsson, and K. Streubel, “Fabrication of a 1.55-μm VCSEL and an InGaAsP-InP HBT from a common epitaxial structure,” IEEE Photonics Technology Lett., vol. 11, no. 4, pp. 403-405, 1999.
[9] Z. Jin, W. Prost, S. Neumann, and F. J. Tegude, “Current transport mechanisms and their effects on the performances of InP-based double heterojunction bipolar transistors with different base structures,” IEEE J. Solid-State Circuits, vol. 84, no. 15, pp. 2910-2912, 2004.
[10] T. Ishibashi and Y. Yamauchi, “A possible near-ballistic collection in an AlGaAs/GaAs HBT with a modified collector structure,” IEEE Trans. Electron Devices, vol. 35, no. 4, pp. 401-404, 1988.
[11] M. E. Kim, A. K. Oki, G. M. Gorman, D. K. Umemoto, and J. B. Camou, “GaAs heterojunction bipolar transistor device and IC technology for high-performance analog and microwave applications,” IEEE Trans. Microwave Theory and Techniques, vol. 37, no. 9, pp. 1286-1303, 1989.
[12] J. H. Tsai, S. Y. Cheng, L. W. Laih, and W. C. Liu, “AlGaAs/InGaAs/GaAs heterostructure-emitter and heterostructure-base transistor (HEHBT),” Electron. Lett., vol. 32, no. 18, pp.1720-1722, 1996.
[13] C. R. Bolognesi, M. M. W. Dvorak, P. Yeo, X. G. Xu, and S. P. Watkins, “InP/GaAsSb/InP double HBTs: a new alternative for InP-based DHBTs,” IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 2631-2639, 2001.
[14] K. B. Thei, J. H. Tsai, W. C. Lui, and W. S. Lour, “Characteristics of functional heterostructure-emitter bipolar transistors (HEBTs),” Solid-State Electron., vol. 39, pp. 1137-1142, 1996.
[15] C. Y. Chen, S. Y. Cheng, W. H. Chiou, H. M. Chuang, R. C. Liu, C. H. Yen, J. Y. Chen, C. C. Cheng, and W. C. Liu, “DC Characterization of an InP/InGaAs Tunneling Emitter Bipolar Transistor (TEBT),” IEEE Tran. Electron Devices, vol. 50, no. 4, pp. 874-879, 2003.
[16] C. Y. Chen, S. Y. Cheng, W. H. Chiou, H. M. Chuang, and W. C. Liu, “A novel InP/InGaAs TEBT for ultralow current operations,” IEEE Electron Devices Lett., vol. 24, no. 3, pp. 126-128, 2003.
[17] K. Kurishima, H. Nakajima, T. Kobayashi, Y. Matsuoka, and T. Ishibashi, “Fabrication and characterization of high-performance InP/InGaAs double-heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 41, no. 8, pp. 1319-1326, 1994.
[18] D. Streit, R. Lai, A. Oki, and A. Gutierrez-Aitken, “InP HEMT and HBT technology and application,” 10th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, pp. 14-17, 2002.
[19] W. C. Wang, H. J. Pan, K. B.Thei, K. W. Lin, K. H. Yu, C. C. Cheng, L. W. Laih, S. Y. Cheng, and W. C. Liu, “Observation of the resonant-tunneling effect and temperature-dependent characteristics of an InP/InGaAs heterojunction bipolar transistor,” Semiconductor Science and Technology, vol. 15, pp. 935-940, 2000.
[20] R. N. Nottenburg, Y. K. Chen, M. B. Panish, D. A. Humphrey, and R. Hamm, “Hot-electron InGaAs/InP heterostructure bipolar transistor with ft of 110 GHz,” IEEE Electron Device Lett., vol. 10, no. 1, pp. 30-32, 1989.
[21] S. Thomas, J. A. Foschaar, C. H. Fields, M. M. Madhav, and M. Sokolich, “Effects of device design on InP-based HBT thermal resistance,” IEEE Trans. Devices and Materials Reliability, vol. 1, no. 4, pp. 185-189, 2001.
[22] C. R. Bolognesi, M. M. W. Dvorak, P. Yeo, X. G. Xu, and S. P. Watkins, “InP/GaAsSb/InP double HBTs: a new alternative for InP-based DHBTs,” IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 2631-2639, 2001.
[23] J. Mba, D. Caffin, A. M. Duchenois, M. Riet, J. L. Benchimol, P. Launay, J. Godin, and A. Scavennec, “Low-power operation of InP-based DHBT's for high bit rate circuit applications: reduction of saturation voltage (Vsat),” International Conference on Indium Phosphide and Related Materials, pp. 651-654, 1998.
[24] H. R. Chen, C. P. Lee, C. Y. Chang, J. S. Tsang, and K. L. Tsai, “The study of emitter thickness effect on the heterostructure emitter bipolar transistors,” J. Appl. Phys, vol. 74, no. 2, pp. 1398-1402, 1993.
[25] J. H. Tsai, S. Y. Chen, W. S. Lour, W. C. Liu, and H. H. Lin, “Investigation of AlInAs/GaInAs heterostructure-emitter-confinement bipolar transistors,” Semiconductor Science and Technology, vol. 12, no. 9, pp. 1135-1139, 1997.
[26] M. M. Jahan and A. F. M. Anwar, “An exact current partitioning and its effect on base transit time in double heterojunction bipolar transistors,” Solid-State Electron., vol. 39, no. 6, pp. 941-948, 1996.
[27] A. Feygenson, D. Ritter, R. A. Hamm, P. R. Smith, R.K. Montgomery, R. D. Yadvish, H. Temkin, and M. B. Panish, “InGaAs/InP composite collector heterostructure bipolar transistors,” Electron. Lett., vol. 28, no. 7, pp. 607-609, 1992.
[28] Z. Abid, S. P. lister, W. R. McKinnon, and E. E. Guzzo, “Temperature dependent DC characteristics of an InP/InGaAs/InGaAsP HBT,” IEEE Electron Device Lett., vol. 15, no. 5, pp. 178-180, 1994.
[29] W. H. Chen, T. P. Chen, C. J. Lee, C. W. Hung, K. Y. Chu, L. Y. Chen, T. H. Tsai, and W. C. Liu, “Comparative study on temperature-dependent characteristics of InP/InGaAs single- and double-heterojunction bipolar transistors,” J. Vacuum Science &; Technology B, vol. 26, no. 2, pp. 618-623, 2008.
[30] E. F. Chor and C. J. Peng, “Composite step-graded collector of InP/InGaAs/lnP DHBT for minimized carrier blocking,” IEEE Electron Device Lett., vol. 32, no. 15, pp. 1409-1410, 1996.
[31] K. Kurishima, H. Nakajima, T. Kobayashi, Y. Matsuoka, and T. Ishibashi, “InP/InGaAs double-heterojunction bipolar transistor with step-graded InGaAsP collector,” Electron. Lett., vol. 29, no. 3, pp. 258-260, 1993.
[32] N. K. Okano, A. Iketani, T. Ijichi, and T. Kikuta, “InGaAs/InP double‐heterojunction bipolar transistors with step graded InGaAsP between InGaAs base and InP collector grown by metal organic chemical vapor deposition,” Applied Phys. Lett., vol. 59, no. 21, pp. 2697-2699, 1991.
[33] P. A. Houston, “High-frequency heterojunction bipolar transistor device design and technology,” J. Electronics &; Communication Engineering, vol. 12, no. 5, pp. 220-228, 2000.
[34] B. Willen, U. Westergren, and H. Asonen, “High-gain, high-speed InP/InGaAs double-heterojunction bipolar transistors with a step-graded base-collector heterojunction”, IEEE Electron Devices Lett., vol. 16, no. 11, pp. 479-481, 1995.
[35] J. H. Tsai, K. P. Zhu, Y. C. Chu, and S. Y. Chiu, “Investigation of InP/InGaAs pnp δ-doped heterojunction bipolar transistor,” Proceeding of the 34th European Solid-State Device Research conference (ESSDERC 2004)., no. 3, pp. 437-439, 2004.
[36] W. C. Liu, D. F. Guo and W. S. Lour, “AlGaAs/GaAs double-heterostructure-emitter bipolar transistor (DHEBT),” IEEE Trans. Electron Devices, vol. 39, no. 12, pp. 2740-2744, 1992.
[37] W. C. Liu, S. Y. Cheng, W. L. Chang, H. J. Pan, and Y. H. Shie, “A new InGaP-GaAs double delta-doped heterojunction bipolar transistor (D3HBT),” International Conference on Microwave and Millimeter Wave Technology Proceedings (ICMMT '98) , pp. 100-103, 1998.
[38] J. Y. Chen, K. W. Lin, C. Y. Chen, H. M. Chuang, C. I. Kao, and W. C. Liu, “On the InP/InGaAs double heterojunction bipolar transistor (DHBT) with emitter tunneling barrier and composite collector structure,” Conference on Optoelectronic and Microelectronic Materials and Devices, pp. 357-360, 2002.
[39] T. P. Chen, W. H. Chen, K. Y. Chu, L. Y. Chen, C. J. Lee, S. Y. Cheng, J. H. Tsai, and W. C. Liu, “Investigation of InP/InGaAs Double Heterojunction Bipolar Transistor (DHBT) with a step-graded InAlGaAs/InP collector structure,” 8th International workshop on Junction Technology, (IWJT '08) Extended Abstracts, pp. 168-171, 2008.
[40] W. S. Lour, W. L. Chang, and L. T. Hung, “Investigation of InGaP/GaAs single and double heterojunction bipolar transistors by doping spike,” Conference on Optoelectronic and Microelectronic Materials and Devices Proceedings, pp. 271-274, 1996.
[41] V. Teppati, Z. Yuping, O. Ostinelli, and C. R. Bolognesi, “Highly Efficient InP/GaAsSb DHBTs With 62% Power-Added Efficiency at 40 GHz,” IEEE Electron Devices, vol. 32, no. 7, pp. 886-888, 2011.
[42] B. R. Wu, M. W. Dvorak, P. Colbus, T. S. Low, and D. D'Avanzo, “High current gain of doping-graded GaAsSb/InP DHBTs,” 23rd International Conference on Indium Phosphide and Related Materials Compound Semiconductor Week (CSW/IPRM), no. 1, pp. 1-3, 2011.
[43] J. Y. Chen, S. Y. Cheng, C. Y. Chen, K. M. Lee, C. H. Yen, S. Y. Fu, S. F. Tsai, and W. C. Liu, “Characteristics of an InP-InGaAs-InGaAsP HBT,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1935-1938, 2004.
[44] S. I. Ferdaus, M. Yeazul, K. Hossain, M. F. Hossain, S. K. Saha, M. I. B. Chowdhury, “Effect of recombination on the base transit time model considering base pushout,” IEEE Regional Symposium on Micro and Nanoelectronics (RSM), no. 14, pp. 14-18, 2011.
[45] N. Palit, A. Dasgupta, S. Ray, P. Chatterjee, “Hole diffusion at the recombination junction of thin film tandem solar cells and its effect on the illuminated current–voltage characteristic,” J. Applied Phys., vol. 88, no. 5, pp. 2853-2861, 2000.

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