臺灣博碩士論文加值系統

隨著半導體製造技術的快速發展，如何有效控制生產過程，降低製程中的變異，以提升良率為晶圓廠重要競爭力要素。在晶圓製造過程中，若機台發生問題、製程參數異常、光罩出現故障等情況發生時，造成晶片的良率過低，晶圓圖會出現某種特殊樣型，藉由晶圓圖所提供的重要線索，工程師可找出製程異常的原因。隨者半導體製造技術的演進、IC線寬的微縮、晶圓尺寸增加及產品多樣化的影響，同一缺陷樣型也將會產生不同樣型大小、不同密度、旋轉角度及雜訊，進而使得晶圓圖樣型分類變得更加困難。若單靠工程師以人工目視的方式辨識晶圓圖樣型，除了需耗費大量時間外，人為主觀因素及對空間樣型辨識能力的差距，造成判斷結果的不同，導致分類缺乏一致性，以致無法使有問題的製程或機台及時排除故障，造成產品良率的損失。以往研究提出以類神經網路來自動辨識故障晶片之樣型，而在此種方法需將二維晶圓圖資料轉換為一維向量的資料才能進行分析，對於相同的樣型但不同的旋轉角度往往會判定成兩種不同的樣型。
本研究發展一套晶圓圖樣型分類架構，以有效解決樣型分類一致性的問題，先利用空間隨機性測試將晶圓圖分為隨機性、重複性與群聚性三種類別，將屬於群聚性的晶圓圖透過資料進退化，減少晶圓圖上之雜訊並強化樣型特徵。藉由各樣型在不同大小、密度或是旋轉角度下其空間相關圖一致性的趨勢，透過萃取空間相關圖上之波形特徵，並利用本研究所提出之分支準則以建構晶圓圖樣型分類樹，以進行晶圓圖樣型分類。本研究將以半導體公司所提供的樣型作為模擬資料依據，進而產生不同的樣型大小、密度、旋轉角度及雜訊之晶圓圖資料以驗證本研究之效度。最後透過5次交互驗證以檢驗研究效度，驗證結果本研究提出之晶圓圖樣型分類模型樣型檢出率及誤判率皆優於動態時間校正分類結果。

With the rapid development of semiconductor manufacturing technology, it is critical to control the production process effectively and minimize process variation for yield enhancement in semiconductor manufacturing industry. To ensure the assignable cause of process variation, one of the most effective ways is to analyze the spatial defect patterns exhibiting on the wafers. Wafer bin map (WBM) can provide important rules for engineers to rapidly find the potential root cause by identifying patterns correctly. As the driven force for semiconductor manufacturing technology, classification of WBM to the correct pattern becomes more difficult because the same pattern may have different size, density, rotation angle and noise degree on the WBM. Nowadays, most companies still rely on engineers’ experiences of visual inspections and personal judgments in the map patterns. This manual approach is not only subjective, lack of justice and consistent standard, but also very time consuming and inefficient.
This study proposes an approach that integrates spatial corrlegram and decision tree to classify the pattern of WBM. First, each map is testing for spatial randomness test to classified into Random, Repeat and Clustered. For the clustered map, applying a data preparation procedure to enhance the signal of cluster and remove the noise. With a spatial correlogram to detect defect pattern, extracting the wave features based on it, to build an classification tree to classify the pattern of WBM. An simulated data sets was conducted for validation. The experimental results show that our method is robust to random noise and has a robust catching rate regardless the pattern size, density and rotation angle of WBM.

目錄 i
表目錄 iii
圖目錄 v
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機與重要性 1
1.3 研究目的與研究範圍 2
1.4 論文結構 3
第二章 文獻回顧 4
2.1 半導體電性測試 4
2.2 空間統計應用於晶圓圖 7
2.2.1 空間隨機性測試 7
2.2.2 空間相關圖（Spatial correlogram） 9
2.3 晶圓圖樣型辨識相關文獻 13
第三章 晶圓圖樣型分類架構 18
3.1 問題定義 20
3.2 資料準備 22
3.3 晶圓圖空間統計分析 23
3.3.1 空間隨機性測試 23
3.3.2 進退化 23
3.3.3 空間相關圖 24
3.3.4 特徵萃取 26
3.4 晶圓圖樣型分類樹建立 29
3.5 結果評估與解釋 32
第四章 分析結果 36
4.1 問題定義 36
4.2 資料準備 37
4.3 晶圓圖空間統計分析 41
4.3.1 空間隨機性測試 41
4.3.2 進退化 42
4.3.3 空間相關圖 43
4.3.4 特徵萃取 44
4.4 晶圓圖樣型分類樹建立 46
4.5 結果評估與解釋 52
4.6 不同晶圓圖分類方法比較 61
4.7 加入新樣型之探討 63
第五章 結論 65
參考文獻 67

林鼎浩（2000），建構半導體製程資料挖礦架及其實證研究，國立清華大學工業工程與工程管理學系碩士論文。
張喬凱（2006），應用類神經方法建構晶圓缺陷點群聚圖案之辨識系統，國立交通大學工業工程與管理學系碩士論文。
劉巧雯（2002），利用資料挖礦方法建構半導體晶圓圖之分群分類系統，國立清華大學工業工程與工程管理學系碩士論文。
簡禎富、施義成、林振銘、陳瑞坤（2005），半導體製造技術與管理，清華大學出版社，新竹。
簡禎富、林鼎浩、劉巧雯、彭誠湧、徐紹鐘、黃佳琪（2002），建構晶圓圖分類之資料挖礦方法及其實證研究，工業工程學刊，19卷2期，頁23-38。
Agresti, A. (1990), Categorical data analysis, John Wiley &; Sons, New York.
Burges, C.J.C. (1998), “A tutorial on support vector machines for pattern recognition,” Data Mining and Knowledge Discovery, Vol. 2, No. 2, pp. 121-167.
Carpenter, G.A. (1988), “The ART of adaptive pattern recognition by self-organization neural network,” Computer, Vol. 21, No. 3, pp. 77-88.
Chao, L.-C. and Tong, L.-I. (2009), “Wafer defect pattern recognition by multi-class support vector machines by using a novel defect cluster index,” Expert System with Applications, Vol. 36, pp. 10158-10167.
Chen, F.-L. and Liu, S.-F. (2000), “A neural-network approach to recognize defect spatial pattern in semiconductor fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 13, No. 3, pp. 366-373.
Chien, C.-F. and Hsu, C.-Y. (2006), “A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing,” Journal of Intelligent Manufacturing, Vol. 17, No. 4, pp. 429-440.
Chien, C.-F., Hsu, C.-Y., and Chang, K.-H. (2011), “Overall wafer effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole,” Computers &; Industrial Engineering, DOI: 10.1016/j.cie.2011.11.024.
Chien, C.-F., Wang, W.-C., and Cheng, J.-C. （2007）, “Data mining for yield enhancement in semiconductor manufacturing and an empirical study,” Expert Systems with Applications, Vol. 33, No. 1, pp. 192-198.
Cunningham, S.P., Spanos, C.J., and Voros K. (1995), “Semiconductor yield improvement : results and best practices,” IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No.2, pp. 103-109.
Ferris-Prabhu, A.V. (1990), “A cluster-modified poisson model for estimating defect density and yield,” IEEE Transactions on Semiconductor Manufacturing, Vol. 3, No.2, pp. 53-59.
Friedman, D.J., Hansen, M.H., Nair, V.N., and James, D.A. (1997), “Model-free estimation of defect clustering in integrated circuit fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No.3, pp. 344-359.
Gart, J.J. and Zweifel, J.R. (1967), “On the bias of various estimators of the logit and its variance with application to quantal bioassay,” Biometrika, Vol. 54, No. 1/2, pp. 181-187.
Hansen, M.H., Friedman, D.J., and Nair, V.J. (1997), “Monitoring wafer map data from integrated circuit fabrication process for spatially clustered defects,” Technometrics, Vol. 39, No. 3, pp. 241-253.
Hsieh, H.-W. and Chen, F.-L. (2004), “Recognition of defect spatial patterns in semiconductor fabrication,” International Journal of Production Economics, Vol. 42, No. 19, pp. 4153-4172.
Hsu, S.-C. and Chien, C.-F. (2007), “Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing,” International Journal of Production Economics, Vol. 107, No. 1, pp. 88-103.
Hwang, J.H. and Kuo, W. (2007), “Model-based clustering for integrated circuit yield enhancement,” European Journal of Operational Research, Vol. 178, No. 1, pp. 143-153.
Jain, A.K., Duin, R.P.W., and Mao, J. (2000), “Statistical pattern recognition: A review,” IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol. 22, No. 1, pp. 4-37.
Kaempf, U. (1995), “The binomial test: A simple tool to identify process problems,” IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No. 2, pp. 160-166.
Kohavi, R. (1995), “A study of cross-validation and bootstrap for accuracy estimation and model selection,” Proceedings of the Fourteenth International Joint Conference on Artificial Intelligence, Vol. 2, No. 12, pp. 1137-1143.
Liu, S.-F., Chen, F.-L., and Lu, W.-B. (2002), “Wafer bin map recognition using a neural network approach,” International Journal of Production Research, Vol. 40, No. 10, pp. 2207-2223.
Meyer, F.J. and Pradhan, D. K. (1989), “Modeling defect spatial distribution,” IEEE Transactions on Computing, Vol. 38, No. 4,pp. 538-546.
Nieddu, L. and Patrizi, G. (2000), “Formal methods in pattern recognition,” European Journal of Operational Research, Vol. 120, No. 3, pp. 459-295.
Ratanamahatana, C.A. and Keogh, E. (2004a), “Making time-series classification more accurate using learned constraints,” Proceedings of the Fourth Siam International Conference On Data Mining, Lake Buena Vista, Florida, pp. 22-24.
Ratanamahatana, C.A. and Keogh, E. (2004b), “Everything you know about dynamic time warping is wrong,” Proceedings of the 10th ACM SIGKDD International Conference Knowledge Discovery and Data Mining, Seattle, WA.
Taam, W. and Hamada, M. (1993), “Detecting spatial effects from factorial experiments: an application from integrated-circuit manufacturing,” Technometrics, Vol. 35, No. 2, pp. 149-160.
Wang, C.-H. (2008), “Recognition of semiconductor defect patterns using spatial filtering and spectral clustering,” Expert System with Applications, Vol. 34, No. 3, pp. 1914-1923.
Yuan, T., Kuo, W. and Bae, S. J. (2011), “Detection of Spatial Defect Patterns Generated in Semiconductor Fabrication Processes,” IEEE Transactions on Semiconductor Manufacturing, Vol. 24, No. 3, pp. 392-403.