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研究生:陳奕文
研究生(外文):Chen, Yi-Wen
論文名稱:奈米級P型高介電/金屬閘極之金氧半電晶體製程最佳化與有效功函數調控的研究
論文名稱(外文):The Studies of Process Optimization and Effective Work Function Tuning on Nano Scale High-k/Metal Gate PMOSFETs
指導教授:林樹均
指導教授(外文):Lin, Su-Jien
學位類別:博士
校院名稱:國立清華大學
系所名稱:材料科學工程學系
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
論文頁數:156
中文關鍵詞:高介電金屬閘極功函數
外文關鍵詞:High kMetal gate electrodeWork function
相關次數:
  • 被引用被引用:0
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  • 收藏至我的研究室書目清單書目收藏:0
為了維持互補型金氧半電晶體(CMOS)持續的微縮尺寸,高介電常數(High-k)介電層與金屬閘電極(Metal gate)技術已成為邏輯CMOS製程技術基礎。然而金屬閘電極的功函數受到材料本質特性限制極易受到傳統高溫回火影響而退化至矽能帶中間。因此金屬閘電極不佳的熱穩定性使得High-k/Metal gate技術無法滿足能帶邊金屬功函數(Band edge metal work function)的要求,特別是p-type MOSFET。
本文研究利用回火 ,Al2O3介電層,以及Al或F離子植入來調控金屬閘極功函數以達到元件特性的需要。作者藉由結合Al以及F離子植入,成功的在前金屬閘極製程下實現能帶變金屬功函數,但也因此出現了些微漏電流增加的壞處。此外,等效氧化層厚度 (EOT) 也會受到前金屬閘極製程必經高溫製程步驟的影響,往下微縮的能力會受到限制。
為了滿足未來元件的應用,引入了可以避免經過高溫製程步驟的後金屬閘極製程。從元件展現出的電性結果包含I/V,C/V以及EDS物性分析來驗證,後金屬閘極製程的確適用於p-type MOSFET能帶邊金屬功函數的需求。而且,藉由在O2氣體中後續回火,可以再更提升金屬功函數而不會增加漏電流以及增厚等效氧化層厚度。又藉由EDS分析金屬閘電極的剖面元素成分特徵,我們發現氧的含量控制了p型閘電極的金屬功函數。
To sustain CMOS transistor continuously scaling, high-k and metal gate technology has become the foundation of logic CMOS technology. Because of the direct tunneling effect, a high gate leakage will be induced in the conventional Poly/SiON gate with a very thin SiON dielectric. Besides, the poly depletion effect also limits Tox_inv for further scaling. Furthermore, the p-type effect work function of a metal gate electrode is easily degraded to Si middle band gap after high temperature activation steps.
To overcome the drawback, in this thesis, we study the use of post dielectric annealing, Al2O3 cap layer, F or Al implantation to modulate work functions of gate metals to meet the p-type MOSFET requirements. By integrating F incorporation and Al implantation in gate first scheme, valence band edge effect work function has been successfully achieved with slightly Jg degradation. Besides, the equivalent oxide thickness (EOT) scaling capability is also restricted in gate first scheme with high temperature thermal budget.
For future device applications, a gate lat scheme suppressing high temperature steps is proposed. Experimental results of I/V, C/V and energy dispersive X-ray spectroscopy (EDS) had evidenced the proposal is available for nano scale p-type MOSFET applications. Valence band edge effective work function and better EOT scaling capability have been demonstrated. By introducing suitable low temperature O2 post metal annealing, work function can be further improved without Jg degradation and EOT penalties. Furthermore, EDS depth profiling through metal gate stacks also revealed that the oxygen content controlled the p-type metal gate work function.
Abstract (Chinese)...................................I
Abstract (English)...................................II
Acknowledgment (Chinese).............................IV
Contents.............................................V
Figure Captions......................................VIII
Chapter 1 Introduction
1-1 Overview.........................................1
1-2 Preface of this thesis...........................5
Chapter 2 Work Function Engineering on TiN/HfO2 Gate Stack
2-1 Introduction.....................................19
2-2 Device Fabrication and Experimental Procedure....21
2-2-1 Fabrication Process for MOS Capacitors.........21
2-2-2 Electrical and Physical Analysis...............23
2-2-3 MOS Capacitor Test Key Design..................24
2-2-4 Effective Work Function Extraction Methodology.25
2-3 Results and Discussions..........................27
2-3-1 TiN thickness and ratio effects for PMOS capacitors...........................................27
2-3-2 PDA and PMA effects for PMOS capacitors........29
2-4 Conclusions......................................31
Chapter 3 Work Function Engineering via Al2O3 cap layer and F Implantation technology
3-1 Introduction.....................................47
3-2 Device Fabrication and Experimental Procedure....48
3-2-1 Fabrication Process for MOS Capacitors.........48
3-2-2 Electrical and Physical Analysis...............50
3-3 Results and Discussions..........................51
3-3-1 Al2O3 cap layer effects........................51
3-3-2 F Implantation technology......................53
3-3-3 F Implantation with Al2O3 cap devices..........56
3-4 Conclusions......................................59
Chapter 4 Work Function Engineering by Al Implantation technology
4-1 Introduction.....................................72
4-2 Device Fabrication and Experimental Procedure....73
4-2-1 Fabrication Process for MOS Capacitors.........73
4-2-2 Electrical and Physical Analysis...............75
4-3 Results and Discussions..........................75
4-3-1 Al Ion Implantation............................75
4-3-2 Al Ion Implantation with F incorporated........80
4-4 Conclusions......................................84
Chapter 5 Work Function Modulation under Gate Last Scheme
5-1 Introduction.....................................98
5-2 Device Fabrication and Experimental Procedure....99
5-2-1 Fabrication Process for MOS Capacitors.........99
5-2-2 Electrical and Physical Analysis...............101
5-3 Results and Discussions..........................102
5-3-1 EWF engineering under low temperature scheme...102
5-3-2 EWF engineering in replacement metal gate scheme .............................................104
5-4 Conclusions......................................106
Chapter 6 Conclusions and Prospects
6-1 Conclusions......................................118
6-2 Prospects........................................120
References...........................................122
Appendix A:Author’s resume..........................141
Appendix B:Author’s publications list...............142

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[4.1] K. Shimishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Kohno, T. Chikyo, H. Kitajima, and T. Arikado, “Physics in Fermi level pinning at the polySi/Hf-based high-k oxide interface”, VLSI Symp. Tech. Dig., pp. 108–109, 2004.
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[5.1] K. Shimishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Kohno, T. Chikyo, H. Kitajima, and T. Arikado, “Physics in Fermi level pinning at the polySi/Hf-based high-k oxide interface”, VLSI Symp. Tech. Dig., pp. 108–109, June 2004.
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[6.1] S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C. -H. Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He*, R. Heussner, R. James, I. Jin, C. Kenyon, S. Klopcic, S. -H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae*, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger, C. Weber**, M. Yang, A. Yeoh, K. Zhang, “A 32nm Logic Technology Featuring 2nd-Generation High-k+ Metal-Gate Transistors, Enhanced Channel Strain and 0.171μm2 SRAM Cell Size in a 291Mb Array”, IEDM Tech. Dig., pp. 941–944, 2008.
[6.2] C. -H. Jan, M. Agostinelli, M. Buehler, Z. -P. Chen, S. -J. Choi, G. Curello, H. Deshpande, S. Gannavaram, W. Hafez, U. Jalan, M. Kang, P. Kolar, K. Komeyli, B. Landau, A. Lake, N. Lazo, S. -H. Lee, T. Leo, J. Lin, N. Lindert, S. Ma, L. McGill, C. Meining, A. Paliwal, J. Park, K. Phoa, I. Post, N. Pradhan, M. Prince, A. Rahman, J. Rizk, L. Rockford, G. Sacks, A. Schmitz, H. Tashiro, C. Tsai, P. Vandervoorn, J. Xu, L. Yang, J.-Y. Yeh, J. Yip, K. Zhang, Y. Zhang, P. Bai, “A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications”, IEDM Tech. Dig., pp. 647–650, 2009.
[6.3] J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick and R. Chau, “Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering”, VLSI Sym. Proc., pp. 178–179, 2006.
[6.4] R. Pillarisetty, B. Chu-Kung, S. Corcoran, G. Dewey, J. Kavalieros, H. Kennel, R. Kotlyar, V. Le, D. Lionberger, M. Metz, N. Mukherjee, J. Nah, W. Rachmady, M. Radosavljevic, U. Shah, S. Taft, H. Then, N. Zelick, and R Chau, “High Mobility Strained Germanium Quantum Well Field Effect Transistor as the P-Channel Device Option for Low Power (Vcc=0.5 V) III-V CMOS Architecture”, IEDM Tech. Dig., pp. 231–232, 2010.
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