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研究生:鄭昕凱
研究生(外文):Cheng, Hsin-Kai
論文名稱:超細微間距三維晶片對晶片堆疊電子構裝之掉落衝擊可靠度分析
論文名稱(外文):Drop Impact Reliability Analysis of Ultra-Fine-Pitch 3D Chip-on-Chip Stacking Electronic Packaging
指導教授:陳文華陳文華引用關係鄭仙志
指導教授(外文):Chen, Wen-HwaCheng, Hsien-Chie
學位類別:碩士
校院名稱:國立清華大學
系所名稱:動力機械工程學系
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:93
中文關鍵詞:可靠度分析掉落試驗
外文關鍵詞:Reliabilitydrop test
相關次數:
  • 被引用被引用:2
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  • 下載下載:0
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隨著可攜式電子產品之輕薄化及高效能需求,進行系統晶片整合以縮小構裝結構尺寸乃必然的趨勢。然而可攜式電子產品常因運送或使用不慎掉落而遭受劇烈衝擊,而造成內部結構的破壞,因此如何增強其抗衝擊能力已成為研發先進構裝之重要課題。
三維晶片對晶片堆疊構裝(3D Chip-on-Chip Stacking Package)不僅可有效使產品結構微小化,接點間距大幅縮小,且可增進電訊傳輸效率,故廣受各界重視。本論文即在利用數值模擬方法與實驗探討工研院所開發之一超細間距三維晶片對晶片堆疊構裝遭受掉落衝擊時之可靠度。此構裝主要由上晶片、下晶片及3,216個銅/鎳/錫銀(Cu/Ni/SnAg)I/O微接點(Micro Bump)所構成,因微接點間距及尺寸均遠小於傳統構裝,故其抗掉落衝擊尤應予重視。
本論文掉落衝擊測試係依據JEDEC(Joint Electron Device Engineering Council)規範進行,掉落衝擊測試機掉落平台自由落下時,產生一近似半弦波之加速度函數,最大加速度為1,500 G,脈衝時間為0.5毫秒。在數值模擬上,本論文則利用LS-DYNA® 有限單元套裝軟體建立一精確可靠之三維有限單元分析模型。為能準確模擬微接點在動態負載下之行為,本論文採用Johnson-Cook本構材料模式(Constitutive Model),以納入應變率及溫度之效應,而動態負載則藉由加速度輸入法(Input-G Method)進行模擬。三維有限單元分析模型計算求得之結果與實驗結果相較頗為脗合。
為評估微接點之疲勞壽命,本論文進而有系統地進行多次不同測試條件下之衝擊疲勞實驗,且經由光學顯微鏡檢測發現,微接點之破壞均發生於錫銀銲材部份。以此疲勞實驗結果為基礎,配合經由有限單元分析獲得之微接點錫銀銲材應變能密度,本論文成功建立了Darveaux 疲勞壽命預估方程式。最後,本論文以所建立之Darveaux疲勞壽命預估方程式對不同的錫銀銲材、填充底膠、介金屬厚度比例及上下晶片厚度等進行參數化分析,以供三維晶片對晶片構裝提升抗衝擊疲勞壽命能力之參考。

With the eager demand of light, thin, and high performance of portable electronic devices, it has been a trend for miniaturizing the structure packaging to integrate the system chip. However, the interior structure of the portable electronic devices could be destroyed as the portable electronics devices are subjected to severe impact due to the conveyance and careless drop. Therefore, it becomes an important issue for the development of advanced packaging to enhance the drop impact resistance of devices.
The three-dimensional (3D) Chip-on-Chip (CoC) Stacking Package receives great attention because of its ability to miniaturize the package, to significantly shorten the interconnect pitch, and to enhance electronic signal transmission efficiency. By the numerical simulation method and the experimental validation, this work aims to study the drop impact reliability of the ultra-fine-pitch 3D CoC Stacking Package which is developed by ITRI. This package consists of a top chip, a bottom chip and 3,216 Cu/Ni/SnAg I/O micro bumps. Because the pitch and size of micro bumps are much smaller than conventional package, it is crucial to pay more attention to its drop impact reliability.
The standard JEDEC(Joint Electron Device Engineering Council) specification is adopted in the drop impact test. As the drop table of drop impact tester freely falls, it produces an almost half-sine wave acceleration function, and its peak acceleration and impulse time are 1,500G and 0.5 ms respectively. As for the numerical simulation, the LS-DYNA finite element software is applied to create an accurate and reliable 3D finite element analysis model. To well simulate the dynamic responses of the micro bumps, a Johnson-Cook constitutive model, which takes into account the effects of strain rate and temperature, is employed, and the input-G method is applied for simulating the dynamic loading. The calculated results of 3D FE modeling match very well with the experimental data.
To evaluate the drop impact fatigue life of the micro bump, this work further systematically carries out a set of drop impact fatigue life experiments under different drop test conditions. Besides, through the optical microscope inspection, it is found that the failure area of micro bumps all occur at the SnAg zone. Based on the obtained fatigue test data and the strain energy density of SnAg of micro bump computed through FE analysis, a Darveaux drop impact fatigue life prediction equation is successfully constructed in this work. Finally, to provide a reference for promoting the drop impact fatigue life resistance for 3D CoC Stacking Package, the effects of different SnAg solders, underfill, IMC thickness ratio and the thickness of the top and bottom chip are investigated through the parametric study.

目錄
摘要 I
目錄 V
表目錄 VIII
圖目錄 IX
第一章、導論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.2-1三維晶片堆疊構裝 2
1.2-2電子構裝掉落衝擊測試 3
1.3研究目標 7
第二章、三維晶片對晶片電子構裝結構 9
2.1 構裝體幾何尺寸與材料性質 9
2.2構裝接合製程 10
第三章、研究方法與分析理論 11
3.1 JEDEC掉落試驗規範 11
3.2加速度輸入法 13
3.3沙漏效應 14
3.4 Johnson - Cook本構材料模式 15
3.5 疲勞壽命預估 16
第四章、實驗內容及程序 18
4.1實驗規劃 18
4.2實驗儀器介紹 19
4.2-1掉落衝擊機台 19
4.2-2 量測系統 19
第五章、結果與討論 21
5.1掉落衝擊測試 21
5.2 掉落衝擊有限單元分析 23
5.2-1 三維有限單元分析模型之建立 23
5.2-2 三維有限單元分析模式之確認與分析 24
5.3掉落衝擊疲勞壽命預估 27
5.4 測試板擺放五顆三維晶片對晶片堆疊構裝體之掉落衝擊分析 29
5.5 填充底膠對三維晶片對晶片堆疊構裝之影響 30
5.6 JEDEC最大加速度與脈衝時間容許誤差分析 31
5.7 微接點於掉落衝擊之參數化分析 32
5.7-1微接點介金屬厚度的影響 33
5.7-2微接點銲材的影響 34
5.7-3錫銀銲材厚度的影響 34
5.8-4上/下晶片厚度效應 35
第六章、結論與未來展望 37
參考文獻 40
附表 45
附圖 57


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