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研究生:黃毓閎
研究生(外文):Huang, Yu-Hung
論文名稱:一個可應用於硬體輔助型軟硬體協同模擬的非侵入式時間同步介面
論文名稱(外文):A Non-Intrusive Timing Synchronization Interface for Hardware-Assisted HW/SW Co-Simulation
指導教授:蔡仁松
指導教授(外文):Tsay, Ren-Song
口試委員:許有進許雅三
口試日期:2012-1-4
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:47
中文關鍵詞:時間同步介面硬體輔助型軟硬體協同模擬
外文關鍵詞:Timing synchronization interfaceHardware-assisted HW/SW co-simulation
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本篇論文提出了一個非侵入式時間同步介面,能使硬體輔助型軟硬體協同模擬基於共享資料型同步的方法達到快速且精準的模擬結果。我們的非侵入式時間同步介面裝置是特別針對元件在不透明環境下模擬所設計的。有了這樣的裝置,我們可以系統化的在匯流排上監測共享資料的存取以及控制硬體輔助型元件的推進時間來達到快速且精準的系統軟硬體協同模擬。實驗結果顯示,我們的方法比起基於傳統時脈型同步的硬體輔助型軟硬體協同模擬方法有了十倍到一百四十倍的加速且維持一樣正確的模擬結果。
This paper proposes using a non-intrusive timing synchronization interface approach to facilitate shared-data synchronization for fast and accurate hardware-assisted HW/SW co-simulation. Our synchronization interface device is specially designed for non-transparent components. With the device, we can systematically monitor shared-data accesses on a bus and control the progressing time of hardware-assisted components for fast and accurate system co-simulation. Experiments show that our approach is 10 to 140 times faster than the cycle-based hardware-assisted co-simulation approach.
1. Introduction
2. Related Work
3. Managing Non-Transparent Components
3.1. Shared-Data Synchronization
3.2. Accurate HW-Assisted Co-Simulation
3.2.1. Identifying Shared-Data Accesses
3.2.2. Calculating Timing
4. Non-Intrusive Synchronization Interface
4.1. Synchronization
4.2. Discussion
5. Experimental Results
6. Conclusion
[1] William D. Bishop and Wayne M. Loucks, “A Heterogeneous Environment for Hardware/Software Cosimulation”, in ANSS’97, April 1997.
[2] Stuart Swan, “SystemC transaction level models and RTL verification”, in DAC‘06, July 2006.
[3] Yuichi Nakamura, Kouhei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, and Takeshi Yoshimura, “A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication”, in DAC‘04, June 2004.
[4] Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, and Ren-Song Tsay, “Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation”, in DATE‘10, March 2010.
[5] Luca Formaggio, Franco Fummi, and Graziano Pravadelli, “A timing-accurate HW/SW co-simulation of an ISS with SystemC”, in CODES+ISSS’04, Sep. 2004.
[6] Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, and Ren-Song Tsay, “An effective synchronization approach for fast and accurate multi-core instruction-set simulation”, in EMSOFT‘09, October 2009.
[7] Franco Fummi, Stefano Martini, Giovanni Perbellini, and Massimo Poncino, “Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC”, in DATE‘04, February 2004.
[8] Dohyung Kim, Youngmin Yi, and Soonhoi Ha, “Trace-driven HW/SW cosimulation using virtual synchronization technique”, in DAC‘05, June 2005.
[9] Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, and Massimo Poncino, “SystemC Cosimulation and Emulation of Multiprocessor SoC Designs”, in Computer, April 2003.
[10] Franco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, and Massimo Poncino, “Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation”, in DATE‘05, March 2005.
[11] Hoeseok Yang, Youngmin Yi, and Soonhoi Ha, “A timed HW/SW coemulation technique for fast yet accurate system verification”, in SAMOS‘09, July 2009.
[12] Jürgen Schnerr, Oliver Bringmann, Alexander Viehl, and Wolfgang Rosenstiel, “High-performance timing simulation of embedded software”, in DAC’08, June 2008.
[13] Kai-Li Lin, Chen-Kang Lo, and Ren-Song Tsay, “Source-level timing annotation for fast and accurate TLM computation model generation”, in ASPDAC‘10, January 2010.
[14] Yi-Len Lo, Mao-Lin Li, and Ren-Song Tsay, “Cycle count accurate memory modeling in system level design”, in CODES+ISSS‘09, October 2009.
[15] David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann Publishers Inc., 2007.
[16] A. Silberschatz, P. B. Galvin, and G. Gagne, Operating System Principles, John Wiley & Sons (Asia) Re Ltd, 2004.
[17] Sudeep Pasricha, Nikil Dutt, and Mohamed Ben-Romdhane, “Extending the transaction level modeling approach for fast communication architecture exploration”, in DAC‘04, June 2004.
[18] Chen-Kang Lo and Ren-Song Tsay, “Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model”, in ASPDAC‘09, January 2009.
[19] AndeStarTM ISA, available at www.andestech.com/p2-2.htm, 2010.
[20] Microtime Computer Inc., www.microtime.com.tw
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