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研究生:游凡緯
研究生(外文):Yu, Fan-Wei
論文名稱:針對確定性多核心指令集模擬之關鍵區間層級的時間同步方法
論文名稱(外文):A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations
指導教授:蔡仁松李哲榮
指導教授(外文):Tsay, Ren-Song
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
論文頁數:41
中文關鍵詞:確定性多核心指令集模擬時間同步
外文關鍵詞:DeterministicMulti-core instruction-set simulationTiming Synchronization
相關次數:
  • 被引用被引用:0
  • 點閱點閱:190
  • 評分評分:
  • 下載下載:8
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文提出了一個針對確定性多核心指令集模擬之關鍵區域層級的時間同步方法,透過同步在每一個鎖的存取,而不是在每一個共享變數的存取,並用一個簡單的鎖使用狀態管理機制,我們的方法可以顯著提高模擬效能,同時使所有關鍵區間執行在一個確定的順序。實驗顯示,我們的方法比起共享變數的同步方法平均快了295%,而我們的方法可以有效地促進系統層級的軟體/硬體協同模擬。
This thesis proposes a Critical-Section-Level timing synchronization approach for deterministic Multi-Core Instruction-Set Simulation (MCISS). By synchronizing at each lock access instead of every shared-variable access and with a simple lock usage status managing scheme, our approach significantly improves simulation performance while having all critical sections executed in a deterministic order. Experiments show that our approach performs in average 295% faster than the shared-variable synchronization approach and the approach can effectively facilitate system-level software/hardware co-simulation.
List of Tables 6
List of Figures 7
Chapter 1 Introduction 9
Chapter 2 Related Work 16
Chapter 3 Critical-Section-Level Timing Synchronization 20
3.1. Identifying Lock Sync Points 22
3.2. Spin-waiting Optimization 25
3.3. Lock Activation 27
3.4. The Critical-Section-Level Simulations 29
Chapter 4 Experimental Results 33
Chapter 5 Conclusion 36
Bibliography 37


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[15] J. Devietti, B. Lucia, L. Ceze, and M. Oskin, “DMP: deterministic shared memory multiprocessing,” in Proceeding of the 14th international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 2009, pp. 85–96.
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