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研究生:陳原逢
論文名稱:N型金氧半場效電晶體選擇性使用源汲極延伸摻雜做為Mask ROM與EEPROM之應用
論文名稱(外文):Characterizations of n‐channel MOSFETs with Tailored Source/Drain Extension for Mask ROM and EEPROM Applications
指導教授:龔正龔正引用關係黃智方
學位類別:博士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:111
中文關鍵詞:非揮發性記憶體罩幕式唯讀記憶體可電氣抹除可程式編碼唯讀記憶體非重疊植入淺淡摻雜
外文關鍵詞:NVMMask ROMEEPROMNOILDD
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非揮發性記憶體(NVM),已開發超過45年並廣泛使用於各類的電子產品。在各種的非揮發性記憶體中,罩幕式可編程唯讀記憶體(Mask ROM)是一個在世界上最便宜的非揮發性記憶體。Mask ROM被廣泛使用於存儲設備,在關閉電源後能夠永久保存資料。而EEPROM,則是目前增長最快的一種非揮發性記憶體產品。本論文提出一種新型的n通道MOSFET具有一個電晶體可儲存兩位元的記憶容量,其使用閘極與源極間之非重疊植入區(NOI)做為Mask ROM和EEPROM的應用。 NOI Mask ROM可以使用輕摻雜汲極(LDD)植入做為編碼。這個簡單的編碼方式是與代工CMOS製程完全兼容。本NOI Mask ROM的特點,包括一個電晶體可儲存兩,基底效應的影響,熱載子的影響和陣列佈局進行研究。通過使用相同的陣列佈局和讀出電路,其電性曲線顯示NOI Mask ROM和NOI EEPROM之間的可以很容易的相互轉換,不需額外的製程與光罩。
Non-volatile Memory (NVM) has been developed and improved in past years, and recently it has been received much attention in mobile or portable applications, such as mobile phones, smart cards and digital camera. First, the history of the Non-volatile Memory (NVM) and the concept of the NVM are introduced. And the typical NVMs, such as EPROM, EEPROM, flash memory are also introduced. However, among various Non-volatile memory types, Mask programmable read-only-memories (Mask ROMs) are one of the cheapest memories. Mask ROMs are widely used memory devices capable of storing permanently information. This thesis presents a novel n-channel MOSFETs with two-bits-per-transistor and gate-to-drain non-overlap implantation (NOI) schemes for Mask ROM and EEPROM applications. The NOI mask ROM can be coded by using the lightly doped drain (LDD) implantation mask and the related processes. This simple coding scheme is fully compatible with industrial CMOS processing. The characteristics of this NOI mask ROM, including two-bit-per-transistor operation, body effect, hot carrier impact and array layouts are investigated. By sharing the same array layout and readout circuit, the potential of NOI devices’ seamless migration between the mask ROM and EEPROM functions are also demonstrated.
Chapter 1 Introduction of Nonvolatile Memory 1
1-1. Introduction of Nonvolatile Memory (NVM) 1
1-2. Objective 3
1-3. Organization of this thesis 4
Chapter 2 Overview of Mask Read Only Memories 7
2-1. Introduction to Mask Read Only Memories 7
2-2. Mask ROM Operation Mechanism 7
2-2-1. Diffusion ROM 9
2-2-2. Implantation Programmed ROM or Flat-cell ROM 10
2-2-3. Contact ROM and Via ROM 12
2-3. NOI Mask ROM 12
2-3-1. Fabrication Process Flow 14
2-3-2. NOI Mask ROM Programming 15
2-3-3. NOI Mask ROM Reading 16
2-4. Summary 19
Chapter 3 The Evaluation of Structure of Charge Storage Type Electric Alterable Nonvolatile Memories 36
3-1. Review of Charge-based Electric Alterable NVMs 36
3-1-1. Charge Trapping Nonvolatile Memory (SONOS) 38
3-1-2. Recent SONOS develop Trends 38
3-2. NOI EEPROM 40
3-2-1. NOI EEPROM Programming 41
3-2-2. NOI EEPROM Erasing 41
3-2-3. NOI EEPROM Reading 42
3-3. Summary 44
Chapter 4 Non-overlapped Implantation Mask ROM Device 54
4-1. NOI Mask ROM Device Characteristics 54
4-2. Effects of Body Bias in Mask ROM Device 56
4-3. Spacer Length Effect and Array Layout 58
4-4. Drain Stress and Hot Carrier Effect 59
4-5. Summary 60
Chapter 5 Non-overlapped Implantation EEPROM Device 72
5-1. NOI EEPROM Two Bits/Cell Operation Principle 72
5-2. NOI EEPROM Device Characteristics 73
5-3. NOI EEPROM Reliability 75
5-4. Summary 78
Chapter 6 Converting Electrical Alterable ROM to Mask ROM 88
6-1. NOI EPROM to NOI Mask ROM 89
6-2. Read-out Window Improvement 90
6-3. Summary 92
Chapter 7 Conclusions and Recommendations for Future Work 100
7-1. Conclusions 100
7-2. Recommendations for Future Work 101
References 102
Publication List 110


References
Chapter 1.
1. Rino Micheloni, Luca Crippa, Alessia Marelli. “Inside NAND Flash Memories”, pp.19, Springer, 2010
2. Jim Hurst “Types RAM and ROM”, www.giac.org/cissp-papers /102.pdf
3. Ashok K. Sharma, “Nonvolatile memories,” Semiconductor memories, IEEE Press, New York, 1996, Chapter 3.
4. Paolo Cappelletti, Carla Golla, Piero Olivo and Enrico Zanoni, “Flash Memories,” Chapter 1, pp. 1-3, Kluwer Academic Publishers, 1999
5. D. Kahng and S.M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol. 46, p.1288, 1967
6. Frohman-Bentchkowsky, D., "A fully decoded 2048bit electrically programmable FAMOS read-only memory", IEEE Journal of Solid-State Circuits, Vol. SC-6, p. 301, 1971
7. H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connell, and R. E. Oleksiak, “The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEEE IEDM Tech. Dig., Washington, D.C., Oct. 1967
8. William D. Brown, Joe E. Brewer, “Nonvolatile semiconductor memory technology : a comprehensive guide to understanding and to using NVSM devices”, IEEE Press, New York, Chapter 1
9. The International Technology Roadmap for Semiconductors (ITRS) : 2011, Process Integration, Devices, and Structures (PIDS). http://www.itrs.net/Links/2011ITRS/2011Chapters/2011PIDS.pdf

Chapter 2
10. W. C. Gong, ” The Study of the Novel Mask ROM,” CYCU Master Thesis, Chu-Li, Taiwan, 2004.
11. R. Cuppens and L. H. M. Sevat, “A 256 kbit ROM with Serial ROM Cell Structure,” IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 3, Jun. 1983.
12. Robert H. Crawford, James R. Biard, “Binary Decoder,” U.S. Pat. No. 3,541,543, Nov. 1970.
13. Robert H. Crawford, “MOSFET in circuit design: metal-oxide- semiconductor field-effect transistors for discrete and integrated- circuit technology,” McGraw-Hill, pages 113-118, 1967
14. Fujio Masuoka, Shoji Ariizumi, Taira Iwase, Michihiro Ono, Norio Endo “An 80 ns 1 Mbit MASK ROM with a New Memory Cell,” IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, Oct. 1984
15. T. Sunaga, "A 30-ns cycle time 4-Mb mask ROM," IEEE Journal of Solid-State Circuits, Vol. SC-29, pp. 1353-1358, Nov. 1994
16. S. Kamuro, Y. Masaki, K. Sano, S. Kimura and Y. Aoki, “High Density CMOS Read-Only Memories for A Handheld Electronics Language Translator,” IEEE Transactions on Consumer Electronics, Vol. CE-27, No. 4, Nov. 1981
17. Star Sung, Thomas Chang, Juei-Lung Chen, “A Nor-Type MLC ROM with Novel Sensing Scheme for Embedded Applications,” Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT’05)
18. Lewis.M. Terman, “FET memory systems,” IEEE Transaction on Magnetics, Vol. mag-6, No.3, pages 584-589, Sept. 1970.
19. Lewis.M. Terman, “MOSFET memory circuit,” Proceedings of the IEEE, Vol. 59, No.7, pages 1044-1058, Jul. 1971
20. Chang-Kiang Kuo, “Method of making implant programmable N-channel ROM,” U.S. Pat. No. 4,230,504, Oct. 1980.
21. “Flat cell ROM Memory Block for Embedded Design Applications,” ALPUS FLASH TECHNOLOGY INC., Feb., 2002
22. Wei Cui, Siliang Wu, "Design of Small Area and Low Power Consumption Mask ROM", Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on, On page(s): 1 - 4, Volume: Issue: , May 30 2007-June 1 2007
23. F. Masuoka, S. Ariizumi, T. Iwase, M. Ono, and N. Endo, “An 80ns 1Mbit Mask ROM with a New Memory Cell”, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, October 1984.
24. Gerald D. Rogers, “Semiconductor memory array with field effect transistors programmable by alternation of threshold voltage,” U.S. Pat. No. 4,059,826, Nov. 1977.
25. H. Kawagoe, N. Tsuji, “Minimum size ROM structure compatible with silicon-gate E/D MOS LSI,” IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 3, Jun. 1976
26. S. Kamuro, Y. Masaki, K. Sano, S. Kimura, “A 256K ROM Fabricated Using n-Well CMOS Process Technology,” IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 4, Aug. 1982
27. C-R. Chang, J-S. Wang, and C-H. Yang “Low Power and High Speed ROM Modules for ASIC Applications,” IEEE Journal of Solid-State Circuits, Vol. SC-36, No. 10, Oct. 2001
28. Harold W. Dozier, “Series read only memory structure,” U.S. Pat. No. 4,142,176, Feb. 1979
29. R. Sasagawa, I. Fukushi, M. Hamaminato, S. Kawashima,” High speed cascode sensing scheme for 1.0V contact programming mask ROM” VLSI Circuits Symp., Pages: 95-96, 17-19 June 1999.
30. David J. McElroy “Method of making a contact programmable double level polysilicon MOS read only memory,” U.S. Pat. No. 4,326,329, Apr. 1982.
31. Meng-Fan Chang, Shu-Meng Yang, "Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.17, Iss.6, pp.758, 2009
32. Meng-Fan Chang, Lih-Yih Chiou, Kuei-Ann Wen, "Crosstalk-insensitive via-programming ROMs using content-aware design framework", IEEE Transactions on Circuits and Systems II Express Briefs, Vol.53, Iss.6, pp.443, 2006
33. Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, "Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements", IEEE Journal of Solid-State Circuits, Vol.45, Iss.SC-10, pp.2142, 2010
34. Taur, Y., Ning, T.H.: “Fundamentals of Modern VLSI Devices.” P.91, Cambridge University Press, Cambridge ,1998
35. James D. Plummer, Michael D. Deal and Peter B. Griffin, “Silicon VLSI Technology”, Department of electrical Engineering Stanford University, Prentice Hall, p.451, 2000
36. Stanley Wolf, “Silicon Processing for the VLSI Era, Vol. 3: The Submicron MOSFET,” Lattice Press, p.591, 2002
37. H. Lee, S.I. Chang, J. Lee and H. Shin, “Characteristics of MOSFET with Non-overlapped Source-drain to Gate,” IEICE Trans. Electron., vol. E85-C, No. 5, pp.1079-1085, 2002
38. S.Thompson, P.Packan*, T.Ghani, M.Stettler*, M.Alavi, I.Post, S.Tyagi, S.Ahmed, S.Yang and M.Bohr “Source/Drain Extension Scaling for O.1pm and Below Channel Length MOSFETS,” Symposium on VLSI Technology, Digest of Technical Papers. Pp 132-133, 1998
39. Zhi-Hong Liu, Chenming Hu, Jian-Hui Huang, Tung-Yi Chan, Min-Chie Jeng, Ping K. Ko, and Y. C. Cheng, “Threshold Voltage Model for Deep-Submicrometer MOSFET’s,” IEEE Transactions on Electron Devices, Vol. 40, Issue: 1, Page(s): 86 – 95, Jan. 1993
40. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finizi, “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Letter., vol. 21, no. 11, pp. 543–545, Nov. 2000.

Chapter 3
41. http://en.wikipedia.org/wiki/Programmable_read-only_memory
42. Roberto Bez, Agostino Pirovano, “Non-volatile memory technologies: emerging concepts and new materials,” Materials Science in Semiconductor Processing, Vol. 7, Issues 4–6, Pages 349–355, 2004
43. P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, “Flash Memory”, Kluwer Academic Publishers, 1999.
44. William D. Brown, Joe E. Brewer, “Nonvolatile semiconductor memory technology: a comprehensive guide to understanding and to using NVSM devices,” New York: IEEE Press, 1998.
45. Rick Shi-Jye Shen et al, “The VLSI Handbook”, in, Wai-Kai Chen (Ed.), Chapter 54, Flash Memories, CRC/IEEE Press, New York. 2000
46. Ashok K. Sharma, ” Advanced semiconductor memories : architectures, designs, and applications,” Wiley-IEEE Press, p. 355, 2003
47. C.-Y. Lu, K.-Y. Hsieh, R. Liu,“Future challenges of flash memory technologies,” Microelectronic Eng., vol. 86 pp.283-286, 2009.
48. S. Ogura, T. Saito, K. Satoh, Y. Baba, N. Ogura, K. Shimeno, T. Ogura, “Twin MONOS: A Nitride based Dual bit Flash Memory,” Non-Volatile Memory Technology Symposium, pp:157-160, 2004
49. Y. K. Lee, S. K. Sung, J. S. Sim, K. W. Song,, J. D. Lee, B. G. Park, S. T. Kang, C. Chung, D. Park, K. Kim, “Scalable 2-bit silicon–oxide–nitride–oxide–silicon (SONOS) memory with physically separated local nitrides under a merged gate,” Solid-State Electronics, Vol. 8, pp. 1771-1775, 2004
50. Y. K. Lee, K. W. Song, J. W. Hyun, J. D. Lee, B.-G. Park, S. T. Kang, J. D. Choe, S. Y. Han, J. N. Han, S. W. Lee, O. I. Kwon, C. Chung, D. G. Park, and K. Kim “Twin SONOS Memory With 30-nm Storage Nodes Under a Merged Gate Fabricated With Inverted Sidewall and Damascene Process,” IEEE ELECTRON DEVICE LETTERS, Vol. 25, No. 5, May 2004.
51. H. Tomyie, T. Terano, K. Nomoto and T. Kobayashi,“A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot electron injection” VLSI Tech. Symp., pp.206-207, 2002.
52. W. C. Wu, T. S. Chao, W. C. Peng, W. L. Yang, J. C. Wang, J. H. Chen, C. S. Lai, T. U. Yang, C. H. Lee, T. M. Hsieh, and J. C. Liou, “Highly Reliable Multi-level and 2-bit/cell Operation of Wrapped-Select-Gate (WSG) SONOS Memory”, IEEE Electron Device Letter., Vol. 28, pp. 214-216, 2007.
53. M. Fukuda, T. Nakanishi, and Y. Nara, “New nonvolatile memory with charge-trapping sidewall,” IEEE Electron Device Letter., Vol. 24, no. 8, pp. 490–492, Jul. 2003.
54. M. Fukuda, T. Nakanishi, and Y. Nara, “Scaled 2 bit/cell SONOS type nonvolatile memory technology for sub-90 nm embedded application using SiN sidewall trapping structure,” in IEDM Tech. Dig., 2003, pp. 909912.
55. C.-S. Hsieh, P.-C. Kao, C.-S. Chiu, C.-H. Hon, C.-C. Fan, W.-C. Kung, Z.-W. Wang and E.S. Jeng, “NVM characteristics of single -MOSFET cells using nitride spacers with gate-to-drain NOI,” IEEE Trans. Electron Devices, Vol. 51, no. 11, pp. 1811–1817, Nov. 2004.
56. T. Ning, C. Osburn and H. Yu, “Emission probability of Hot Electrons from Silicon into Silicon Dioxide”, J. Appl. Phys., Vol. 48, pp. 286, 1977.
57. C. Hu, S. Tam, F. Hsu, P. Ko, T. Chan and K. Terrill, “Hot Electron Induced MOSFET Degradation-Model, Monitor and Improvement”, IEEE Trans. Electron Devices, ED-32, pp. 375, 1985.
58. M. S. Liang, C. Chang, W. Yang, C. Hu and R. W. Brodersen, “Hot Carriers Induces Degradation in Thin Gate Oxide MOSFETs”, Int. Electron Devices Meeting, pp. 186, 1983.
59. Richard S. Muller, Theodore I. Kamins, Mansun Chan, ”Device Electronics for Integrated Circuits, 3rd Edition,” John Wiley &; Sons, chapter.10, pp. 490-501, 2003
60. G. Groeseneken, R. Degraeve, T. Nigam, G. Van den bosch, H. E. Maes, “Hot carrier degradation and time-dependent dielectric breakdown in oxides”, Microelectronic Engineering 49, pp. 27, 1999.T.Y. Chan, J. Chen, P.K. Ko and C. Hu, “The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,” International Electron Device Meeting, Vol.33, pp. 718-721, 1987
61. T. Endoh, R. Shirota, M. Momodomi, and F. Masuoka “An Accurate Model of Subbreakdown Due to Bandto-Band Tunneling and Some Applications,” IEEE Transactions on Electron Devices, Vol. 37, No. I , Jan. 1990
62. K. Hasnat, C. F. Yeap, S. Jallepalli, W. K. Shin, S. A. Hareland, V. M. Agostinelli, A. F. Tasch and C. M. Maziar, “A Pseudo-Lucky electron model for simulation of electron fate current in submicron NMOSFET’s”, IEEE Transaction on Electron Devices, Vol.43, No.8, pp.1264-1273, Aug. 1996.
63. S. Tam, P. K. Ko, C. Hu, and R. S. Muller, “Correlation between substrate and gate currents in MOSFET’s,” IEEE Transactions on Electron Devices, Vol. 29, No. 11, pp. 1740-1744, Nov, 1982.
64. C. Hu, “Lucky-electron model of channel hot electron emission,” International Electron Devices Meeting, vol. 25, pp. 22-25, 1979.
65. P. E. Cotrell, R. R. Troutman, and T. H. Ning, “Hot Electron Emission in N-Channel IGFET’s,” IEEE Journal of Solid State Circuits, Vol. 14, p.442, 1979.
66. L. Selmi and D. Esseni, “A Better Understanding of Substrate Enhanced Gate Current in VLSI MOSFET’s and Flash Cells-Part II: Physical Analysis”, IEEE Transactions on Electron Devices, Vol.46, No.2, pp.376-381, Feb. 1999.
67. M. Lenzinger and E. H. Snow, “Fowler-Noedhieim Tunneling into Thermally Grown SiO2,” Journal of Applied Physics, Vol. 40, Issue. 1, Jan. 1969
68. O. Semenov, A. Pradzynski, and M. Sachdev, “Impact of Gate Induced Drain Leakage on Overall Leakage of Submicrometer CMOS VLSI Circuits,” IEEE Transaction on Semiconductor Manufacturing, Vol. 15, pp. 9, Feb. 2002.
69. K. N. Yang, H. T. Huang, M. C. Chang, C. M. Chu, Y. S. Chen, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Jang, D. C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in P+ poly-gate PMOS-FETs with ultra-thin gate oxides,” IEEE Transaction on Electron Devices, vol. 47, pp. 2161-2166, Nov., 2000.
70. W. C. Lee, and C. Hu, “Modeling CMOS tunneling currents through ultra-thin gate oxide due to conduction and valence band electron and hole tunneling,” IEEE Transaction on Electron Devices, vol. 48, pp. 1366-1373, July 2001.
71. L. Larcher, P. Pavan, and B. Eitan, “On the Physical Mechanism of the NROM Memory Erase,” IEEE Transaction on Electron Devices, vol. 51, No. 10, pp. 1593-1599, Oct. 2004.

Chapter 4
72. Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits: Analysis and Design”, McGraw-Hill Professional, 2003
73. Janai M, Eitan B, Shappir A, et al. Data retention reliability “model of NROM nonvolatile memory products.” IEEE Trans. Device Mater. Rel., 2004, 4(4): 404-414.
74. E.S. Jeng , C.S. Chiu, C.H. Hung, P.C. Guo, J.C. Fan, C.S. Hsieh, K.M. Lin, H.C. Hsu, and Y.F. Chen, “Performance Improvement and Scalability of Non-Overlapped Implantation nMOSFETs with Charge -Trapping Spacers as Non-Volatile Memories”, IEEE Transactions on Electron Devices, Vol. 54, No. 12, Page(s):3299- 3307, Dec. 2007
75. E. S. Jeng, P.-C. Kuo, C.-S. Hsieh, C.-C. Fan, K.-M. Lin, H.-C. Hsu, and W.-C. Chou, “Investigation of programming charge distribution in nonoverlapped implantation nMOSFETs,” IEEE Transaction on Electron Devices, vol. 53, no. 10, pp. 2517–2524, Oct. 2006.

Chapter 5
76. W. J. Tsai, N. K. Zous, M. H. Chou, S. Huang, H. Y. Chen, Y. H. Yeh,M. Y. Liu, C. C. Yeh, T.Wang, J. Ku, and C.Y. Lu, “Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell,” Proc. Int. Rel. Phys. Symp., pp.522-526. 2004
77. E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Characterization of channel hot electron injection by the subthreshold slope of NROM device,” IEEE Electron Device Letter, vol. 22, no. 11, pp. 556–558, Nov. 2001.
78. S. S. Ang, Y. I. Shi, and W. D. Brown, J. Appl. Phys., 73, 2397 (1993).
79. 18. K. Lehovec and A. Fedotowsky, Appl. Phys. Lett, 32, 335 (1978).
80. P. Candelier, F. Mondon, B. Guillaumot, G. Reimbold, and F. Martin, IEEE Electron Device Lett., 18, 306 (1997).
81. Ching-Yuan Ho, Y. F. Chen, C.W. Ho,Wei. Chang, S.W. Chou, and J. Gong, “Retention Behavior Using Si3N4 Spacers Charging on NMOSFETs for Future Nonvolatile Memory Application,” Journal of The Electrochemical Society, vol.158 (5) H536-H539, 2011
82. C.-H. Hsiao, S. W. Chou, K. M. Peng, Y. F. Chen and E. S. Jeng, “Study of Charge Retention Reliability Model in Non-overlapped Implantation nMOSFETs, “ 2011 International Electron Devices and Materials Symposium , Nov. , 2011

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