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研究生:李文山
研究生(外文):Lee, Wen-Shan
論文名稱:建構於4H-SiC碳化矽半絕緣基板上之橫向型高電壓元件設計與製作
論文名稱(外文):Design and Fabrication of 4H-SiC Lateral High-Voltage Devices on Semi-Insulating Substrates
指導教授:黃智方龔正龔正引用關係
指導教授(外文):Huang, Chih-FangGong, Jeng
學位類別:博士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
論文頁數:119
中文關鍵詞:碳化矽橫向型元件半絕緣基板高壓絕緣閘極雙極電晶體金氧半場效電晶體接面場效電晶體PN 二極體載子生命週期
外文關鍵詞:silicon carbidelateral devicesemi-insulating substratehigh-voltageIGBTMOSFETJFETPN diodecarrier lifetime
相關次數:
  • 被引用被引用:0
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中文摘要
本文主要研究建構在半絕緣基板之4H-SiC橫向高電壓 RESURF元件之關鍵設計參數,並經由模擬及實際元件製作來測試驗證。表面電荷, 場平板, 電荷平衡狀況對崩潰電壓之影響等皆列入模擬.從模擬結果來看,場平板可降低電場集中現象而表面電荷在電荷平衡上扮演關鍵地位.相較於單漂移區之設計,雙漂移區RESURF架構可產生額外之電場峰值, 因而可將具100微米漂移區之元件崩潰電壓從 5880 V提升至8000 V.
我們製作了建構於半絕緣基板上之橫向高電壓元件 PN二極體, 接面場效電晶體, 金氧半場效電晶體,絕緣閘極雙極電晶體以驗證我們所提出結構之優點.製程中我們加入N2O退火,載子生命週期改善等不同製程以強化順向導通特性. 為了解高壓與低壓元件整合於單一晶片之可行性, 我們製作了一顆互補金氧半場效電晶體反向器並測試其性能.
本研究主要達成之成果為:
1. 製作出100微米雙漂移區橫向接面場效電晶體具有導通電阻454 mΩ-cm2及崩潰電壓4200 V,達到 FOM值 38.8 MW/cm2 .
2. 製作出40微米單漂移區橫向金氧半場效電晶體具有導通電阻115 mΩ-cm2及崩潰電壓2460 V,達到 FOM值 52 MW/cm2 .
3. 首次製作出建構於半絕緣基板上之4H-SiC高電壓橫向絕緣閘極雙極電晶體. 80微米單漂移區橫向絕緣閘極雙極電晶體達到導通電阻425 mΩ-cm2及崩潰電壓2670 V之性能.利用載子生命週期改善製程達成PN二極體與絕緣閘極雙極電晶體之初步順向特性改善. PN二極體順向導通電壓降低5.5%, 絕緣閘極雙極電晶體共基極電流增益達到0.3.另外本文也對溫度,注入效率與載子生命週期對絕緣閘極雙極電晶體性能之影響做了研究分析及歸納
Abstract
Critical design issues for 4H-SiC lateral devices on a semi-insulating substrate with a RESURF structure have been investigated and verified through simulation and experiment. The dependence of breakdown voltage on surface charges, field plates, and charge imbalance conditions was simulated. From simulation results, it is evident that the field plates help reducing the electric field crowding and the surface charges play a critical role in the charge imbalance analysis. Compared to single zone, a two-zone RESURF structure is able to create an additional peak in the electric field profile, thus increasing the Breakdown Voltage ( BV) from 5880 to 8000 V for a device with a drift region length of 100 μm.
The lateral High-Voltage devices on semi-insulating substrate including PN diode, JFET, MOSFET, and IGBT were fabricated and characterized to verify the advantages of the proposed structure. Various process improvement, such as N2O annealing, lifetime enhancing, was also done to better the forward characteristic. To check the feasibility of integrating High-voltage with low-voltage devices on a chip, a CMOS inverter was fabricated and tested. The main achievements of this study are
(1) The two-zone lateral JFET with Ld of 100 μm exhibits a specific on-resistance of 454 mΩ-cm2 and a BV of 4200 V, having a figure of merit of 38.8 MW/cm2.
(2) The single-zone lateral MOSFET with Ld of 40 μm shows a Ron,sp of 115 mΩ-cm2 and a BV of 2460 V. The FOM is as high as 52 MW/ cm2.
(3) A 4H-SiC lateral High-Voltage IGBT on semi-insulating substrate is demonstrated for the first time. An Ron,sp of 425 mΩ-cm2 and a BV of 2670 V was obtained for sin-gle-zone lateral IGBT with Ld of 80 μm. PN diodes and IGBTs with carrier lifetime enhancement exhibit a preliminary improvement in forward characteristics. For PN, a 5.5% voltage drop reduction was reached. For IGBT, a common base current gain of 0.3 was obtained. The influence of temperature, injection efficiency and lifetime on IGBT performance was investigated and summarized.

Contents

Chapter 1 Introduction

1.1 Wide band gap material -silicon carbide
1.2 Lattice structure of silicon carbide
1.3 Electronic properties of SiC
1.3.1 Incomplete ionization
1.3.2 Carrier lifetime
1.3.3 Carrier mobility
1.4 Ohmic contact
1.5 High purity semi-insulating substrate
1.6 Review of SiC high-voltage devices

Chapter 2 Design and Simulation of 4H–SiC Lateral High-
Voltage Devices on a Semi-Insulating Substrate

2.1 Lateral devices on conventional conducting substrates
2.2 Design optimization for lateral devices on semi-
insulating substrate
2.2.1 Single-zone RESURF device
2.2.2 Two-zone RESURF device

Chapter 3 Fabrication of 4H–SiC Lateral High-Voltage
Devices on a Semi-Insulating Substrate

3.1 Process steps used for fabrication of the high-voltage
lateral PN, JFET, MOSFET, IGBT and the low-voltage CMOS
inverter
3.2 Fabrication of lateral PN diodes
3.3 Fabrication of lateral JFETs
3.4 Fabrication of lateral MOSFETs
3.5 Fabrication of lateral IGBTs
3.6 Fabrication of CMOS

Chapter 4 Characterization for 4H–SiC Lateral High-Voltage
Devices on a Semi-Insulating Substrate

4.1 Characterization for test structures and CMOS inverter
4.1.1 Test structures characterization
4.1.2 Temperature dependence of forward conduction
characteristics of the test structures
4.1.3 CMOS inverter characterization
4.2 Characterization for lateral PN diodes
4.2.1 Forward characteristics of lateral PN diode at room
temperature
4.2.2 Temperature dependence of the forward
characteristics of lateral PN diodes
4.2.3 Off-state blocking characteristics of lateral PN
diodes
4.2.4 Discussion
4.3 Characterization for lateral JFETs
4.3.1 Forward characteristics for lateral JFET
4.3.2 Blocking characteristics for lateral JFETs
4.3.3 Discussion
4.4 Characterization for lateral MOSFETs
4.4.1 Forward characteristics at room temperature
4.4.2 Dependence of forward characteristic on temperature
4.4.3 Blocking characteristic
4.4.4 Discussion
4.5 Characterization for lateral IGBTs
4.5.1 Room temperature forward characteristics
4.5.2 Dependence of forward characteristic on temperature
4.5.3 The effects of lifetime improvement on forward
characteristics
4.5.4 The effects of buffer doping on forward
characteristics
4.5.5 Forward blocking capability
4.5.6 Discussion

Chapter 5 Conclusion and Future Works

References
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