臺灣博碩士論文加值系統

本研究之目的在於將實驗室高效能的像素架構、類比數位轉換器以及週邊電路整合於同一晶片中，以降低雜訊與節省晶片面積，使其能方便應用於多功能消費性電子產品中。本研究使用標準的TSMC 0.18μm SiGe BiCMOS標準製程，在Full HD的規格下，嘗試實現具有30frame/s的畫面更新率、高動態偵測範圍的單晶片攝像系統。
在類比數位轉換器方面，因考量未來對於高畫素的需求，影像感測器使用行並列的輸出方式，故使用高線性度、架構簡單且低功率損耗的單斜率架構，做為每一行的類比數位轉換器，設計解析度為十位元，取樣頻率為50kHz，每一行的功率損耗小於150uW。

The purpose of this research is to integrate a high-performance pixel architecture which designed by our laboratory, an analog to digital converter (ADC) and peripheral circuits in chip. It can reduce noise, save chip area, and easily be applied to the multi-function consumer electronics. Therefore, this study will design a front-end circuit for a Full HD camera-on-chip system with 30 frames per second, wide sensing dynamic range in standard TSMC 0.18μm SiGe BiCMOS technology.
Considering the demand of higher pixel resolution in the future, this paper presents a CMOS imager with column-level ADC. The implemented ADC uses a single-slope architecture which features high linearity, simple structure and low power consumption. Design of resolution is 10bit, sampling rate is 50kHz, and power consumption is less than 150uW for each column.

第一章 前言 1
1.1研究背景與發展現況 1
1.2研究動機 4
1.3論文章節架構 5

第二章 CMOS影像感測器之特性與技術 6
2.1 CMOS影像感測器的基本操作與原理 6
2.2 CMOS影像感測器的特性 8
2.3 CMOS影像感測器常見之像素架構 11
2.4類比數位轉換器的特性參數 15
2.5 CMOS影像感測器常見之類比數位轉換器 18

第三章 電路設計 24
3.1 SIGE感光二極體[11] 25
3.2對數型主動像素感測電路 27
3.3單斜率類比數位轉換器 31
3.3.1 Fixed Pattern Noise抑制電路設計 34
3.3.2斜坡產生器 39
3.3.3比較器 40
3.3.4十位元計數器與移位暫存器 41
3.4 偏壓電路設計 43
3.5 時脈控制電路設計 45
3.5.1時脈產生器 46
3.5.2電路控制開關設計 47

第四章 模擬結果 49
4.1像素電路模擬 49
4.2 CDS電路模擬 51
4.3斜坡訊號產生器模擬 52
4.4單斜率ADC電路模擬結果 54
4.5影像感測器數位輸出模擬結果 57
4.6時脈控制電路模擬 59
4.7晶片佈局 59
4.8文獻比較表 62

第五章 量測結果與探討 63
5.1 量測系統的建立 63
5.1.1 量測儀器 64
5.2 8X8影像感測器量測結果 65
5.2.1偏壓與數位控制電路量測結果 65
5.2.2單一畫素量測結果 66
5.2.3 ADC量測結果 68
5.2.4系統量測結果 72
5.3 量測結果討論 72

第六章 總結 77
6.1 成果整理 77
6.2 後續研究改進之建議 77

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