臺灣博碩士論文加值系統

在積體電路整合技術上，如晶片系統（SOC）、系統層級封裝（SIP）及三維晶片（3D IC）等，先進的整合技術容易造成溫度升高和電壓落差的現象，此現象輕則造成電路速度或操作頻率變緩慢，嚴重可造成晶片運算錯誤或無法驅動的結果發生。因此，一套能即時線上監控晶片內部溫度和工作電壓的方法是必須的。在我們的研究中，利用環狀震盪器（Ring Oscillator）來達成這項目的。以往，環狀震盪器經常被使用於積體電路中製程變動的監測器。然而，環狀震盪器的震盪週期或頻率會因為三大因素的改變而影響，分別是製程變動（Process Variation）、工作電壓(Supply Voltage)及溫度(Temperature)。在此研究中，我們提出一套便於積體電路使用的環狀震盪器以達成共同多因素考量的線上監測方法，它不僅可提供晶片內部製程變異的程度，同時也可在正常操作環境中監測溫度和電壓落差（IR-drop）。為了達到這個目的，此方法透過自動化輔助軟體來達成下列兩項方案：（1）PVT感知的環狀震盪器週期模組建立與分析，即針對給予或特定的環狀震盪器在不同的操作溫度、和電壓落差之下會反應出不同震盪週期，再將其記錄下來成週期模組，以及（2）在考慮製程變動下，針對積體電路內的工作電壓和操作溫度進行追蹤偵測，而最終將輸出晶片觀察點上的溫度波形與電壓落差波形。

The ring oscillator has long been used as a process monitor inside an IC. However, its clock period is jointly affected by the PVT (Process, Voltage, and Temperature) conditions. In this work, we present a low-cost methodology that can make a ring oscillator an even more versatile monitor – for not only the process status, but also the temperature and the IR-drop traces in normal operation. To achieve this goal, our methodology heavily relies on the support of the software to perform two tasks - (1) PVT-aware clock period modeling of a given ring oscillator, and (2) PVT analysis that derives the temperature trace and the IR-drop trace inside an IC under monitoring considering process variation.

Abstract i
摘要 ii
誌謝 iii
Content iv
List of Figures vi
List of Tables vii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 5
Chapter 2 Preliminaries 6
Chapter 3 Proposed Methodology 10
3.1 Overview 10
3.2 PVT-Aware Ring-Oscillator Clock Period Modeling 14
3.2.1 VT-Aware RO-CP Modeling 14
3.2.2 Process Calibration 16
3.3 PVT Analysis 19
3.3.1 PVT Analysis Flow 20
Chapter 4 Experimental Results 24
4.1 The Resolution of Our PVT Monitor 24
4.2 The Accuracy of Our Process Calibration 26
4.3 Evaluation Method 27
4.4 First Testcase: GCD 28
4.5 Second Testcase: AES 31
4.6 Related Works Summary 34
Chapter 5 Conclusion 36
Bibliography 37

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