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研究生:黃信元
研究生(外文):Huang, Hsin-Yuan
論文名稱:具自適應式電容切換技術之低功耗非同步漸近式類比數位轉換器之設計與製作
論文名稱(外文):The Design and Implementation of Power-Efficient Asynchronous SAR ADC with Adaptive Digital-to-Analog Converter Switching Technique
指導教授:謝志成謝志成引用關係
指導教授(外文):Hsieh, Chin-Cheng
口試委員:謝志成盧志文陳巍仁洪浩喬
口試日期:2012-3-6
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:84
中文關鍵詞:連續漸進式類比至數位轉換器 Successive
外文關鍵詞:Successive Approximation analog-to-
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本論文描述了兩個應用低功耗生醫電路之超低功耗10位元非同步漸近式類比數位轉換器(SAR ADC) 的設計。所提出的兩個類比數位轉換器之供給電源為0.7V至1V, 採樣頻率則為250kS/s至1MS/s。所提出的非同步漸近式類比數位轉換器利用多種技巧來提高ADC功率效率。首先提出一個以分裂式電容切換方式為基礎的自適應式電容切換技術(adaptive digital-to-analog converter switching, ADS),以減少平均切換電容數和來提高電容切換效率。也利用高度匹配的金屬類型單位電容來降低單位電容值進一步減少電容切換功耗。最後,利用動態SAR控制器來減少電晶體數目進一步的優化數位和類比電路之間的功耗權衡。
為驗證本電路,本論文利用0.18微米混合式訊號CMOS製程來實現此二顆實驗晶片。第一個實驗晶片操作在1V供給電源和500kS/ s的採樣率。在接近Nyquist頻率所測得的有效位元數(ENOB),是9.24位元。總功耗為14.2微瓦,等效的figure of merit(FoM)則為47fJ/Conversion-step。
第二個實驗晶片則是第一顆實驗晶片的優化版本。操作電源從0.7V到0.9V。在操作電源和取樣頻率為0.9V和1MS / s時的ENOB和總功耗分別為9.33位元和7.84微瓦。由此產生的FoM則是12.1fJ/conversion-step。當操作電源和取樣頻率為降低至0.7V和250KS/ s時的總功耗只有1.07微瓦。由此產生的ENOB和FOM在接近Nyquist的輸入頻率分別是8.8位元和9.58fJ/conversion-step。

Chapter 1 Inroduction 11
1.1 Architecture Selection 12
1.2 Performance Metrics of SAR ADCs 14
1.2.1 Resolution 14
1.2.2 Quantization Noise 14
1.2.3 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) 15
1.2.4 Signal-to-Noise Ratio (SNR) 15
1.2.5 Effective Resolution 16
1.2.6 Figure of Merit (FoM) 16
1.3 Motivation 16
1.4 Target Specifications 17
1.5 Thesis Organizations 18
Chapter 2 Successive Approximation Register (SAR ) ADC Overview 19
2.1 Global Operation of SAR ADC 19
2.1.1 Sources of Error 20
2.2 Sampling Network 22
2.2.1 On-Resistance of MOS Switch 22
2.2.2 Charge Injection and Clock Feedthrough 24
2.2.3 Thermal Noise 25
2.3 Digital-to-Analog Converter 26
2.3.1 Binary Weighted DAC 26
2.3.2 DAC Parasitic Capacitance and Capacitor Mismatch 27
2.4 Device Mismatch of Comparator 28
2.5 Successive Approximation Register 29
2.6 Summary 30
Chapter 3 Circuit Design Considerations 31
3.1 Differential SAR ADC 31
3.2 CDAC Switching Energy 33
3.2.1 Energy Saving CDAC Switching in [7] 35
3.2.2 Monotonic Switching Procedure in [18] 38
3.2.3 Concepts of Adaptive DAC switching 40
3.3 Sample and Hold Design Consideration 41
3.4 Comparator Design Consideration 42
3.5 SAR Control Design Consideration 42
3.6 Summary 43
Chapter 4 Circuit Design 44
4.1 Capacitive DAC Design 44
4.1.1 Adaptive DAC Switching Operation 46
4.2 Sampling Network Design 50
4.3 Comparator Design 51
4.4 Asynchronous SAR Logic and DAC Control Logic Design 53
4.5 Enhancements of Prototype 1 56
4.6 Summary 58
Chapter 5 Measurements Results 59
5.1 Measurement Environment Setup 59
5.2 Measurements of First Prototype 60
5.2.1 Static Performance 61
5.2.2 Dynamic Performance 62
5.2.3 Performance Summary and Comparison 64
5.3 Measurement results of Second Prototype 65
5.3.1 Static Performance 67
5.3.2 Dynamic Performance 68
5.3.3 Performance Summary and Comparison 73
5.4 Summary 74
Chapter 6 Conclusion and Future work 76
6.1 Conclusion 76
6.2 Future Work 76
6.2.1 Comparator with Offset Compensation and Supply Boost 77
6.2.2 Sampling Network Improvement 78
Bibliography 80

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