跳到主要內容

臺灣博碩士論文加值系統

(3.237.38.244) 您好!臺灣時間:2021/07/24 17:28
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:吳家榮
論文名稱:矽晶圓上製作高效能鍺電子元件
論文名稱(外文):High Performance Ge-based Electron Devices Fabricated on Si Substrate
指導教授:巫勇賢
學位類別:博士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:160
中文關鍵詞:電晶體電阻式記憶體快閃記憶體
外文關鍵詞:germaniumtransistorRRAMflash memory
相關次數:
  • 被引用被引用:0
  • 點閱點閱:166
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文主要分成兩大架構,第一部份著重於如何解決以往在整合鍺基板製作邏輯元件上遇到的困難點,例如:如何於矽晶圓上形成高品質的鍺磊晶層以及氧化層、解決n型鍺/金屬接面的費米能階釘扎現象。利用氧化矽鍺還原的方式,在第二、三章中成功於在矽晶圓上形成高濃度單晶鍺薄膜以及高品質之二氧化矽氧化層,其中包含利用單晶矽鍺氧化還原或是非晶鍺薄膜氧化還原兩個方式,以上這兩個方式替將來鍺電子元件應用上提供了一個更便利且經濟的選擇,此外氧化層經過氨氣氮化後再處以額外的一氧化二氮氣體處理可以的成功提高薄膜介電常數且改善元件漏電特性。第四章利用四氟化碳電漿處理修補鍺介面斷鍵來改善n型鍺/金屬接面的費米能階釘札現象。論文的第二部分著重於新穎鍺電子元件開發,利用先前的研究基礎成功於矽晶圓上製作鍺類型快閃記憶體以及鍺電阻式記憶體。相較於傳統矽類型快閃記憶體,鍺類型快閃記憶體能有更快的操作速度,並且在可靠度上也有相當不錯的電性表現,並發現利用鍺向外擴散摻雜穩定二氧化鋯電荷捕捉層的結晶態能有效的提高電荷捕捉層的介電係數以及提供更多電荷儲存的空間,詳細內容述於第五、六章。第七章探討鍺電阻式記憶體的製作,利用鍺的高介面陷阱特性進而改變氧空缺移動的現象。所有實驗結果總結於第八章。傳統矽電子元件在尺寸微縮已遇到極大的挑戰,鍺電子元件在未來高速元件應用上是個相當具有潛力的選擇,本論文解決了以往於整合鍺基板製作邏輯元件的種種困難,並且成功的於矽晶圓開發出高效能鍺電子元件,能相容於現行的互補式金氧半電晶體製程並應用於新世代鍺電子元件開發。
Chapter 1
Introduction 1
1.1 Motivation 1
1.2 Integration Issue on Ge Bulk 2
1.2.1. Material Property: 3
1.2.2. Native Oxide Quality 4
1.2.3. Source/Drain Formation and Junction Leakage 4
1.2.4. Fermi Level Pinning 5
1.3 Organization of the Thesis 5
1.4 References 8
Chapter 2
Thermal Gate SiO2 for Ge Metal-Oxide-Semiconductor Capacitors Fabricated on Si Substrate 17
2.1 Abstract 17
2.2 Introduction 17
2. 3 Overview of Epi-Ge on Si substrate 18
2.3.1. Epi-Ge on Si substrate 18
2.3.2. Heteroepitaxial Ge Layer on Si Grown by MHAH 19
2.3.3. Strained Ge on Relaxed Si Grown by UHVCVD 20
2.3.4. Ultrathin Pure Ge on Si Substrate Grown by UHVCVD 21
2.3.5. Strained Ge Grown on Virtual Ground by UHVCVD 21
2.3.6. Strained GOI on Si Fabricated by Condensation Technique 22
2.3.7. GOI Through Bonding Process 23
2. 4 Motivation 23
2. 5 Experiment 23
2.6 Results and Discussion 24
2.6.1. Physical Property Analysis 24
2.6.2. Gate Leakage Current 26
2.6.3. C-V Characteristic 26
2. 7 Conclusion 27
2. 8 References 28
Chapter 3
Thermal SiO2 Gated Ge Metal-Oxide-Semiconductor Capacitor on Si Substrate Formed by Thin Amorphous Ge Oxidation and Thermal Annealing 43
3.1 Abstract 43
3.2 Introduction 43
3.2.1. Direct High-k Dielectric on Ge 45
3.2.2. Low Temperature Oxide (LTO) 45
3.2.3. Germanium Oxynitride (GeOxNy) 46
3.2.4. Germanium Dioxide (GeO2) 46
3. 3 Motivation 47
3.4 Experiment 47
3.5 Results and Discussion 48
3.5.1. Physical Property Analysis 48
3.5.2. C-V Characteristic 50
3.5.3. F-N Plot Fitting 50
3.6 Conclusion 51
3.7 References 52
Chapter 4
Impact of Fluorine Treatment on Fermi Level Depinning for Metal/Germanium Schottky Junctions 63
4.1 Abstract 63
4.2 Introduction 63
4.2.1. Inserting a Thin Insulator 64
4.2.2 Surface Passivation 65
4.3 Motivation 65
4.4 Experiment 65
4.5 Results and discussion 66
4.5.1. J-V Characteristics and XPS Analysis 66
4.5.2 CF4 Passivation with Different Metal/n-Ge Contact 68
4.5.3. Contact Resistance and J-V Curve of Al/p-Ge Contact 69
4.6 Conclusion 70
4.7 References 71
Chapter 5
Ge-Based Silicon-Oxide-Nitride-Oxide-Silicon-Type Nonvolatile Memory Formed on Si Substrate79
5.1 Abstract 79
5.2 Introduction 79
5.2.1. SONOS Type Nonvolatile Memory 79
5.2.2. Fowler-Nordheim (F-N) Tunneling 80
5.2.3. Endurance 81
5.2.4. Retention 81
5.3 Motivation 82
5.4 Experiment 84
5.5 Results and Discussion 86
5.5.1. Device Structure and TEM Picture 86
5.5.2. C-V Hysteresis Window 86
5.5.3. P/E Transient Characteristics 87
5.5.4. Band Diagram for Program and Erase Operation 88
5.5.6. Leakage Current and Tbd measurement 90
5.5.7. Endurance Performance 90
5.5.8. Data Retention Performance 91
5.6 Conclusion 92
5.7 References 93
Chapter 6
Ge-Based Nonvolatile Memory Formed on Si Substrate with Ge-Stabilized Tetragonal ZrO2 as Charge Trapping Layer 104
6.1 Abstract 104
6.2 Introduction 104
6.2.1. High-k Material Charge Trapping Layer 104
6.2.2. Crystalline Dielectric (Tetragonal ZrO2) 105
6.3 Motivation 106
6.4 Experiment 107
6.5 Results and discussion 109
6.5.1. XRD Analysis of ZrO2/GeO2/Ge Stack. 109
6.5.2 XPS Analysis of ZrO2/GeO2/Ge Stack 109
6.5.3. C-V Characterization of Capacitor Devices 111
6.5.4 C-V Hysteresis of Memory Device 111
6.5.5. Charge Storage Effect of Memory Devices 112
6.5.6. C-V Hysteresis Memory Window 112
6.5.7. Program and Erase Characteristics 113
6.5.8 Endurance Characteristic 114
6.5.9. Retention Characteristic and Leakage Current 115
6.6 Conclusion 116
6.7 References 118
Chapter 7
ZrTiOx-Based Resistive Memory with Metal/Insulator/Semiconductor Structure Formed on Ge Layer 135
7.1 Abstract 135
7.2 Introduction 135
7.2.2. RRAM Switching Characteristic 137
7.2.3 Cations Migration 137
7.2.4. Joule Heating 138
7.2.5 Oxygen Vacancy Migration 138
7.3 Motivation 138
7.4 Experiment 139
7.5 Results and discussion 139
7.5.1 Resistive Switching Characteristics of ZTO/Ge Sample 139
7.5.2. Resistive Switching Characteristics of ZTO/Si Sample 141
7.5.3. Conduction Mechanism Fitting 142
7.5.4. Endurance and Retention Performance 143
7.6 Conclusion 143
7.7 References 145
Chapter 8
Conclusion 155
Chapter 9
Future Work 158
Publication List 159

Chapter 1
1.G. E. Moore, “Cramming more components onto integrated circuits”, Electronics, vol. 38, p.114, 1965.'
2.C. Claeys and E. Simoen, “Germanium-based technologies from material to devices”, first edition, Elsevier, UK, 2007.
3.K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson, M. Bohr, M, “Delaying forever: uniaxial strained silicon transistors in a 90 nm CMOS technology,” in VLSI Symp. Tech. Dig., 2004, pp. 50-51.
4.P. P. Cea, S. Deshpande, H. Ghani, T. Giles, M. Golonzka, O. Hattendorf, M. Kotlyar, R. Kuhn, K. Murthy, A. Ranade, P. Shifren, L. Weber, and C. Zawadzki, “High performance Hi-k + metal gate strain enhanced transistors on (110) silicon,” in IEDM Tech. Dig., 2008, pp. 1-4.
5.Smith, C.E. Adhikari, H. Lee, S. H. Coss, B. Parthasarathy, S. Young, C. Sassman, B. Cruz, M. Hobbs, C. Majhi, P. Kirsch, and P. D. Jammy, “Dual channel FinFETs as a single high-k/metal gate solution beyond 22 nm node,” in IEDM Tech. Dig., 2009, pp. 1-4.
6.M. Lundstrom, “Elementary scattering theory of the Si MOSFET,” IEEE Electron Device Lett., vol. 26, pp. 151-154, 2005.
7.O. J. Gregory, E. E. Crisman, L. Pruitt, D. J. Hymes, and J. J. Rosenberg, “Electrical characterization of some native insulators on germanium,” in Proc. Mater. Res. Soc. Symp., vol. 76, 1987, pp. 307–311.
8.G. E. Stillam, V. M. Robins, and N. Tabatable, “Ill-V compound semiconductor devices: optical detectors,” IEEE Trans. Electron Devices, vol. 31, pp. 1643-1655, 1984.
9.C. O. Chui, A. K. Okyay, and K. C. Saraswat, “Effective dark current suppression with asymmetric MSM photodetectors in group IV semiconductors,” IEEE Photonics Tech. Lett., vol. 15, pp. 1585-1587, 2003.
10.C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, “A sub-400 °C germanium MOSFET technology with high-k dielectric and metal gate,” in IEDM Tech. Dig., 2002, pp. 437-440.
11.W. P. Bai, N. Lu, J. Liu, A. Ramirez, D. L. Kwong, D. Wristers, A. Ritenour, L. Lee, and D. Antoniadis, “Ge MOS characteristics with CVD HfO2 gate dielectrics and TaN gate electrode,” in VLSI Symp. Tech. Dig., 2003, pp. 121-122.
12.N. Wu, Q. Zhang, C. Zhu, D. S. H. Chan, A. Du, N. Balasubramanian, M. F. Li, A. Chin, J. K. O. Sin, and D. L. Kwong, “A TaN-HfO2-Ge pMOSFET with novel SiH4 surface passivation,” IEEE Electron Device Lett., vol. 25, pp. 631-633, 2004.
13.T. Low, Y. T. Hou, M. F. Li, C. Zhu, A. Chin, G. Samudra, and D. L. Kwong, “Investigation of performance limits of germanium double-gated MOSFETs,” in IEDM Tech. Dig., 2003, pp. 691-694.
14.H. Shang, H. O. Schmidt, K. K. Chan, M. Copel, J. A. Ott, P. M. Kozlowski, S. E. Steen, S. A. Cordes, H. S. P. Wong, E. C. Jones, and W. E. Haensch, “High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric,” in IEDM Tech. Dig., 2002, pp. 441-444.
15.A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L. Kwong, and D. A. Antoniadis, “Epitaxial strained germanium p-MOSFETs with HfO2 gate dielectric and TaN gate electrode,” in IEDM Tech. Dig., 2003, pp. 433-436.
16.M. L. Lee, C. W. Leitz, Z. Cheng, A. J. Pitera, T. Langto, M. T. Currie, G. Taraschi, E. A. Fitzgerald, and D. A. Antoniadis, “Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates,” Appl. Phys. Lett., vol. 79, pp. 3344-3346, 2001.
17.H. Shang, J. O. Chu, S. Bedell, E. P. Gusev, P. Jamison, Y. Zhang, J. A. Ott, M. Copel, D. Sadaa, K. W. Guarini, and M. Ieong, “Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS,” in IEDM Tech. Dig., 2004, pp. 157-160.
18.A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, “Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si,” IEEE Electron Device Lett., vol. 26, pp. 311-313, 2005.
19.C. C. Yeo, B. J. Cho, F. Gao, S. J. Lee, M. H. Lee, C.Y. Yu, C. W. Liu, L. J. Tang, and T. W. Lee, “Electron mobility enhancement using ultrathin pure Ge on Si substrate,” IEEE Electron Device Lett., vol. 26, pp. 761-763, 2005.
20.D. S. Yu, K. C. Chiang, C. F. Cheng, A. Chin, C. Zhu, M. F. Li, and D. L. Kwong, “Fully silicided NiSi:Hf-LaAlO3/SG-GOI n-MOSFETs with high electron mobility,” IEEE Electron Device Lett., vol. 25, pp. 559-561, 2004.
21.D. S. Yu, A. Chin, C. C. Laio, C. F. Lee, C. F. Cheng, W. J. Chen, C. Zhu, M. F. Li, W. J. Yoo, S. P. McAlister, and D. L. Kwong, “3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-k dielectric on 1P6M-0.18 μm-CMOS,” in IEDM Tech. Dig., 2004, pp. 181-184.
22.T. Tezuka, N. Sugiyama, and S. Takagi, “Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction,” Appl. Phys. Lett., vol. 79, pp. 1798-1800, 2001.
23.T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, K. C. Saraswat, “Low defect ultra-thin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT),” in VLSI Symp. Tech. Dig., 2005, pp. 81-83.
24.J. P. Xu, P. T. Lai, C. X. Li, X. Zou, and C. L. Chan, “Improved electrical properties of Germanium MOS capacitors with gate dielectric grown in wet-NO ambient,” IEEE Electron Device Lett., vol. 27, pp. 439-441, 2006.
25.P. C. McIntyre, D. Chi, C. O. Chui, H. Kim, K. I. Seo, K. C. Saraswat, R. Sreenivasan, T. Sugawara, F. S. Aguirre Testado, and R. M. Wallace, “Interface layers for high-k/Ge gate stacks: Are they necessary?,” ECS Trans. vol. 3, pp. 519-530, 2006.
26.T. Sugawara, Y. Oshima, R. Sreenivasan, and P. C. Mclntyre, “Electrical properties of germanium/metal-oxide gate stacks with atomic layer deposition grown hafnium-dioxide and plasma-synthesized interface layers,” Appl. Phys. Lett., vol. 90, p. 112912, 2007.
27.C. O. Chui, K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, “Activation and diffusion studies of ion-implanted p and n dopants in germanium,” Appl. Phys. Lett., vol. 16, pp. 3275-3277, 2003.
28.C. O. Chui, L. Kulig, J. Moran, and W. Tsai, “Germanium n-type shallow junction activation dependences,” Appl. Phys. Lett., vol. 87, p. 091909, 2005.
29.C. H. Poon, L. S. Tan, B. J. Cho, and A. Y. Dub, “Dopant loss mechanism in n+/p germanium junctions during rapid thermal annealing,” J. Electrochem. Soc., vol. 12, p. G895, 2005.
30.S. J. Whang, S. J. Lee, F. Gao, N. Wu, C. X. Zhu, J. S. Pan, L. J. Tang, and D. L. Kwong, “Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3 and thin AlN) and TaN/HfO2 gate stack,” in IEDM Tech. Dig., 2004, pp. 307-310..
31.A. Dimoulas, P. Tsipas, and A. Sotiropoulos, “Fermi-level pinning and charge neutrality level in germanium,” Appl. Phys. Lett., vol. 89, p. 252110, 2006.
32.C. O. Chui, F. Ito, and K. C. Saraswat, “Nanoscale germanium MOS dielectrics-part I: germanium oxynitrides,” IEEE Electron Device Lett., vol. 53, pp. 1501-1508, 2006.
33.M. Houssa, T. Conard, F. Bellenger, G. Nicholas, G. Mavrou, Y. Panayiotatos, A. Dimoulas, M. Meuris, M. Caymax, and M. M. Heyns, “Electrical properties of atomic-beam deposited GeO1−xNx/HfO2 Gate Stacks on Ge,” J. Electrochem. Soc., vol. 153, p. G1112, 2006.

Chapter 2
1.K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson, M. Bohr, M, “Delaying forever: uniaxial strained silicon transistors in a 90 nm CMOS technology,” in VLSI Symp. Tech. Dig., 2004, pp. 50-51.
2.M. Lundstrom, “Elementary scattering theory of the Si MOSFET,” IEEE Electron Device Lett., vol. 26, pp. 151-154, 2005.
3.O. J. Gregory, E. E. Crisman, L. Pruitt, D. J. Hymes, and J. J. Rosenberg, “Electrical characterization of some native insulators on germanium,” in Proc. Mater. Res. Soc. Symp., vol. 76, 1987, pp. 307–311.
4.G. E. Stillam, V. M. Robins, and N. Tabatable, “Ill-V compound semiconductor devices: optical detectors,” IEEE Trans. Electron Devices, vol. 31, pp. 1643-1655, 1984.
5.C. O. Chui, A. K. Okyay, and K. C. Saraswat, “Effective dark current suppression with asymmetric MSM photodetectors in group IV semiconductors,” IEEE Photonics Tech. Lett., vol. 15, pp. 1585-1587, 2003.
6.A. Nayfeh, C. O. Chui1, K. C. Saraswat, and T. Yonehara, “Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: surface roughness and electrical quality,” Appl. Phys. Lett., vol. 85, pp. 2815-2817, 2004.
7.A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, “Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si,” IEEE Electron Device Lett., vol. 26, pp. 311-313, 2005.
8.T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, K. C. Saraswat, “Low defect ultra-thin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT),” in VLSI Symp. Tech. Dig., 2005, pp. 81-83.
9.C. C. Yeo, B. J. Cho, F. Gao, S. J. Lee, M. H. Lee, C.Y. Yu, C. W. Liu, L. J. Tang, and T. W. Lee, “Electron mobility enhancement using ultrathin pure Ge on Si substrate,” IEEE Electron Device Lett., vol. 26, pp. 761-763, 2005.
10.M. L. Lee, C. W. Leitz, Z. Cheng, A. J. Pitera, T. Langto, M. T. Currie, G. Taraschi, E. A. Fitzgerald, and D. A. Antoniadis, “Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates,” Appl. Phys. Lett., vol. 79, pp. 3344-3346, 2001.
11.M. T. Currie, S. B. Samavedam, T. A. Langdo, C. W. Leitz, and E. A. Fitzgerald, “Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing,” Appl. Phys. Lett., vol. 72, pp. 1718-1720, 1998.
12.T. Tezuka, N. Sugiyama, and S. Takagi, “Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction,” Appl. Phys. Lett., vol. 79, pp. 1798-1800, 2001.
13.F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, and B. S. Meyerson, “Oxidation studies of SiGe,” J. Appl. Phys. Lett., vol. 65, pp. 1724-1728, 1989.
14.T. Tezuka, N. Sugiyama, T. Mizuno, M. Suzuki, and S. Takagi, “A novel fabrication technique of ultrathin and relaxed SiGe buffer Layers with high Ge fraction for sub-100 nm strained silicon-on-insulator MOSFETs,” Jpn. J. Appl. Phys. Lett., vol. 40, pp. 2866-2874, 2001.
15.K. Brunner, H. Dobler, G. Abstreiter, H. Schafer, and B. Lustig, “Molecular beam epitaxy growth and thermal stability of Si1-xGex layers on extremely thin silicon-on-insulator substrates,” Thin Solid Films., vol. 40, pp. 2866-2874, 2001.
16.D. S. Yu, A. Chin, C. C. Laio, C. F. Lee, C. F. Cheng, W. J. Chen, C. Zhu, M. F. Li, W. J. Yoo, S. P. McAlister, and D. L. Kwong, “3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-k dielectric on 1P6M-0.18 μm-CMOS,” in IEDM Tech. Dig., 2004, pp. 181-184.
17.C. J. Tracy, P. Fejes, N. Theodore, P. Maniar, E. Johnson, A. J. Lamm, A. M. Paler, I. J. Malik, and P. Ong, “Germanium-on-insulator substrates by wafer bonding,” J. Electron. Mater., vol. 33, pp. 886-892, 2004.
18.Y. H. Wu, W. J. Chen, A. Chin, and C. Tsai, “The effect of native oxide on epitaxial SiGe from deposited amorphous Ge on Si,” Appl. Phys. Lett., vol. 74, p. 123176, 1999.
19.W. S. Liu, J. S. Chen, D. Y. C. Lien, and M. A. Nicolet, “Ge epilayer of high quality on a Si substrate by solid‐phase epitaxy,” Appl. Phys. Lett., vol. 63, pp. 1405-1407, 1993.
20.W. S. Liu, M. A. Nicolet, T. K. Carns, and K. L. Wang, “Epitaxial Ge layers on Si via GexSi1-xO2 reduction: The roles of the hydrogen partial pressure and the Ge content,” J. Electron. Mater., vol. 23, pp. 437-440, 1994.
21.M. Koh, W. Mizubayashi, K. Iwamoto, H. Murakami, T. Ono, M. Tsuno, T. Mihara, K. Shibahara, S. Miyazaki, and M. Hirose, “Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current,” IEEE Trans. Electron Devices, vol. 48, pp. 259-264, 2001.
22.Y. H. Wu, E. Hsieh, R. Kuo, S. Lai, and C. L. Ku, “Extending storage dielectric scaling limit by reoxidizing nitrided NO dielectric for trench DRAM,” IEEE Electron Device Lett., vol. 26, pp. 66-68, 2005.
23.Y. H. Wu and Albert Chin,“Gate oxide integrity of thermal oxide grown on high temperature formed Si0.3Ge0.7,” IEEE Electron Device Lett., vol. 21, pp. 113-115, 2000.
24.Y. H. Wu, A. Ku, and J. F. Wang, “Boron-retarded gate dielectric formed by dry oxidation of thermal nitride,” J. Electrochem. Soc., vol. 151, pp. F1-F6, 2004.
25.L. K. Han, J. Kim, G. W. Yoon, J. Yan, and D. L. Kwong,“High quality oxynitride gate dielectrics prepared by reoxidation of NH3-nitrided SiO2 in N2O ambient,” IEEE Electronics Lett., vol. 31, pp. 1196-1198, 1995.

Chapter 3

1.A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L. Kwong, and D. A. Antoniadis, “Epitaxial strained germanium p-MOSFETs with HfO2 gate dielectric and TaN gate electrode,” in IEDM Tech. Dig., 2003, pp. 433-436.
2.O. J. Gregory, E. E. Crisman, L. Pruitt, D. J. Hymes and J. J. Rosenberg, “Electrical characterization of some native insulators on germanium,” Mat. Res. Soc. Symp. Proc., vol. 76, pp. 307-311, 1987.
3.M. D. Jack, J. Y. M. Lee, and H. Lefevre, “DLTS measurements of a germanium MIS interface,” J. Electron. Mater., vol. 10, pp. 571–589, 1981.
4.E.E. Crisman, J.I. Lee, P.J. Stiles and O.J. Gregory, “Characterisation of n-channel germanium MOSFET with gate insulator formed by high-pressure thermal oxidation,” Electron. Lett., vol. 23, pp. 8-10, 1987.
5.Y. Wang, Y. Z. Hu and E. A. Irene, “Electron cyclotron resonance plasma and thermal oxidation mechanisms of germanium,” J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 12, pp. 1309-1314, 1994.
6.V. Craciun, I. W. Boyd, B. Hutton and D. Williams, “Characteristics of dielectric layers grown on Ge by low temperature vacuum ultraviolet-assisted oxidation,” Appl. Phys. Lett., vol. 75, pp. 1261-1263, 1999
7.R. S. Johnson, H. Niimi and G. Lucovsky, “New approach for the fabrication of device-quality Ge/GeO2/SiO2 interfaces using low temperature remote plasma processing,” J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 18, pp. 1230-1234, 2000.
8.D. Kuzum, A. J. Pethe, T. Krishnamohan, Y. Oshima, Y. Sun, J. P. McVittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, “Interface-engineered Ge (100) and (111), N- and P-FETs with high mobility,” in IEDM Tech. Dig., 2007, pp. 723-726.
9.C. O. Chui, F. Ito, and K. C. Saraswat, “Nanoscale germanium MOS dielectrics-part I: germanium oxynitrides,” IEEE Trans. Electron Devices, vol. 53, pp. 1501-1508, 2006.
10.J. P. Xu, P. T. Lai, C. X. Li, X. Zou, and C. L. Chan, “Improved electrical properties of germanium MOS capacitors with gate dielectric grown in wet-NO ambient,” IEEE Electron Device Lett., vol. 27, pp. 439-441, 2006.
11.C. On Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, “Atomic layer deposition of high-k dielectric for germanium MOS applications - substrate surface preparation,” IEEE Electron Device Lett., vol. 25, pp. 274-276, 2004.
12.K. H. Kim, R. G. Gordon, A. Ritenour, and D. A. Antoniadis, “Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-k oxide/tungsten nitride gate stacks,” Appl. Phys. Lett., vol. 90, p. 212104, 2007.
13.S. J. Whang, S. J. Lee, F. Gao, N. Wu, C. X. Zhu, J. S. Pan, L. J. Tang, and D. L. Kwong, “Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3 and thin AlN) and TaN/HfO2 gate stack,” in IEDM Tech. Dig., 2004, pp. 307-310.
14.N. Wu, Q. Zhang, C. Zhu, D. S. H. Chan, A. Du, N. Balasubramanian, M. F. Li, A. Chin, J. K. O. Sin, and D. L. Kwong, “A TaN-HfO2-Ge pMOSFET with novel SiH4 surface passivation,” IEEE Electron Device Lett., vol. 25, pp. 631-633, 2004.
15.Y. Kamata, Y. Kamimuta, T. Ino, R. Iijima, M. Koyama and A. Nishiyama, “Influences of annealing temperature on characteristics of Ge p-channel metal oxide semiconductor field effect transistors with ZrO2 gate dielectrics,” Jpn. J Appl. Phys., vol. 45, pp. 5651-5656, 2006.
16.C. O. Chui, S. Ramanathan, B. B. Triplett, P. C. McIntyre, and K. C.Saraswat, “Germanium MOS capacitors incorporating ultrathin high-k gate dielectric,” IEEE Electron Device Lett., vol. 23, pp. 473-475, 2002.
17.M. L. Lee, C. W. Leitz, Z. Cheng, A. J. Pitera, T. Langto, M. T. Currie, G. Taraschi, E. A. Fitzgerald, and D. A. Antoniadis, “Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates,” Appl. Phys. Lett., vol. 79, pp. 3344-3346, 2001.
18.K. Kita, T. Takahashi, H. Nomura, S. Suzuki, T. Nishimura, and A. Toriumi, “Control of high-k/germanium interface properties through selection of high-k materials and suppression of GeO volatilization,” Appl. Surf. Sci., vol. 254, pp. 6100-6105, 2008.
19.C. H. Lee, T. Tabata, T. Nishinura, K Nagashio, K. Kita, and A. Toriumi, “Ge/GeO2 interface control with high-pressure oxidation for improving electrical characteristics,” Appl. Phys Express., vol. 2, p. 071404, 2009.
20.H. Shang, J. O. Chu, S. Bedell, E. P. Gusev, P. Jamison, Y. Zhang, J. A. Ott, M. Copel, D. Sadana, K. W. Guarini, and M. Ieong, “Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS,” in IEDM Tech. Dig., 2004, pp. 157-160.
21.T. Krishnamohan, Z. Krivokapic, K. Uchida1, Y. Nishi, and K. C. Saraswat, “Low defect ultra-thin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT),” in VLSI Symp. Tech. Dig., 2005, pp. 82-83.
22.D. S. Yu, C. H. Huang, A. Chin, C. Zhu, M. F. Li, B. J. Cho, and D. L. Kwong, “Al2O3-Ge-on-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates,” IEEE Electron Device Lett., vol. 25, pp. 138-140, 2004.
23.Y. H. Wu, J. R. Wu, and M. L. Wu, “Thermal gate SiO2 for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate,” Appl. Phys. Lett., vol. 91, p. 093503, 2007.
24.A. Chin, W. J. Chen, R. H. Kao, B. C. Lin, T. Chang, C. Tsai, and J. C. M. Huang, “Ultra-thin oxide with atomically smooth interfaces,” in Proc. VTSA., Tech. Dig., 1997, pp. 177-181.
25.A. Kanjilal, J. Lundsgaard Hansen, P. Gaiduk, A. Nylandsted Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett., vol. 82, pp. 1212-1214, 2003.
26.M. Zacharias, R. Weigand, B. Dietrich, F. Stolze, J. Biasing, P. Viet, T.Drusedau, and J. Christen, “A comparative study of Ge nanocrystals in SixGeyOz alloys and SiOx/GeOy multilayers,” J. Appl. Phys., vol. 81, pp. 2384-2390. 1997.
27.H. Jin, S. K. Oh and H. J. Kang, “Electronic structure of ultrathin Si oxynitrides,” Surf. Interface Anal., vol. 38, pp. 1564-1567, 2006.
28.A. J. Hong, M. Ogawa, K. L. Wang, Y. Wang, J. Zou, Z. Xu, and Y. Yang, “Room temperature Si δ-growth on Ge incorporating high-k dielectric for metal oxide semiconductor applications,” Appl. Phys. Lett., vol. 93, p. 023501, 2008.
29.M. Koh, W. Mizubayashi, K. Iwamoto, H. Murakami, T. Ono, M. Tsuno, T. Mihara, K. Shibahara, S. Miyazaki, and M. Hirose, “Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current,” IEEE Trans. Electron Devices, vol. 48, pp. 259-264, 2001.
30.M. Perego, G. Scarel, M. Fanciulli, I. L. Fedushkin, and A. A. Skatova, “Fabrication of GeO2 layers using a divalent Ge precursor,” Appl. Phys. Lett., vol. 90, p. 162115, 2007.
31.A. Ohta, H. Nakagawa, H. Murakami, S. Higashi, and S. Miyazaki, “Photoemission study of ultrathin GeO2/Ge heterostructures formed by UV-O3 oxidation,” e-J. Surf. Sci. Nanotech., vol. 4, pp. 174-176, 2006. 

Chapter 4

1.C. O. Chui, K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, “Activation and diffusion studies of ion-implanted p and n dopants in germanium,” Appl. Phys. Lett., vol. 83, pp. 3275-3277, 2003.
2.A. Dimoulas, P. Tsipas, A. Sotiropoulos, and E. K. Evangelou, “Fermi-level pinning and charge neutrality level in germanium,” Appl. Phys. Lett., vol. 89, p. 252110, 2006.
3.T. Maeda, K. Ikeda, S. Nakaharai, T. Tezuka, N. Sugiyama, Y. Moriyama, and S. Takagi, “High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide schottky source/drain,” IEEE Electron Device Lett., vol. 26, pp.102-104, 2005.
4.Y. Zhou, M. Ogawa, X. Han, and K. L. Wang, “Alleviation of Fermi-level pinning effect on metal/germanium interface by insertion of an ultrathin aluminum oxide,” Appl. Phys. Lett., vol. 93, p. 202105, 2008.
5. R. R. Lieten, S. Degroote, M. Kuijk, and G. Borghs, “Ohmic contact formation on n-type Ge,” Appl. Phys. Lett., vol. 92, p. 022106, 2008.
6.A. V. Thathachary, K. N. Bhat, N. Bhat, and M. S. Hegde, “Fermi level depinning at the germanium schottky interface through sulfur passivation,” Appl. Phys. Lett., vol. 96, p. 152108, 2010.
7.Y. Zhou, W. Han, Y. Wang, F. Xiu, J. Zou, R. K. Kawakami, and K. L. Wang, “Investigating the origin of Fermi level pinning in Ge Schottky junctions using epitaxially grown ultrathin MgO films,” Appl. Phys. Lett., vol. 96, p. 102103, 2010.
8.T. Nishimura, K. Kita, and A. Toriumi, “Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface,” Appl. Phys. Lett., vol. 91, p. 123123, 2007.
9.T. Nishimura, K. Kita, and A. Toriumi, “A significant shift of schottky barrier heights at strongly pinned metal/germanium interface by inserting an ultra-thin insulating film,” Appl. Phys. Express., vol. 1, p. 051406, 2008.
10.M. Kobayashi, A. Kinoshita, K. Saraswat, H.-S. P. Wong, and Y. Nishi, “Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application,” J. Appl. Phys., vol. 105, p. 023702, 2009.
11.A. M. Roy, J. Y. J. Lin, and K. C. Saraswat, “Specific contact resistivity of tunnel barrier contacts used for Fermi level depinning,” IEEE Electron Device Lett., vol. 31, pp. 1077-1079, 2010.
12.R. Xie, M. Yu, M. Y. Lai, L. Chan, and C. Zhu, “High-k gate stack on germanium substrate with fluorine incorporation,” Appl. Phys. Lett., vol. 92, p. 163505, 2008.
13.S. Kurtin, T. C. McGill, and C. A. Mead, “Fundamental transition in the electronic nature of solids,” Phys. Rev. Lett., vol. 22, p. 1433-1436, 1969.
14.Y. H. Wu, W. J. Chen, A. Chin, and C. Tsai, “The effect of native oxide on epitaxial SiGe from deposited amorphous Ge on Si,” Appl. Phys. Lett., vol. 74, pp. 528-530, 1999.
15.Y. H. Wu, J. R. Wu, and M. L. Wu, “Thermal gate SiO2 for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate,” Appl. Phys. Lett., vol. 91, p. 093503, 2007.
16.Y. H. Wu, M. L. Wu, Y. S. Lin, and J. R. Wu, “Electrical characteristics of thermal-SiON-gated Ge p-MOSFET formed on Si substrate,” IEEE Electron Device Lett., vol. 30, pp. 72-74, 2009
17.Y. H. Wu, J. R. Wu, M. L. Wu, L. L. Chen, and Y. S. Lin, “Ge-based Silicon-oxide-nitride-oxide-silicon-type nonvolatile memory formed on Si substrate,” J. Electrochem. Soc., vol. 156, p. H944, 2009.
18.T. M. Pan and Z. H. Li, “High-performance CF4 plasma treated polycrystalline silicon thin-film transistors using a high-k Tb2O3 gate dielectric,” Appl. Phys. Lett., vol. 96, p. 113504, 2010.
19.Y. T. Chen, H. Zhao, Y. Wang, F. Xue, F. Zhou, and J. C. Lee, “Effects of fluorine incorporation into HfO2 gate dielectrics on InP and In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors,” Appl. Phys. Lett., vol. 96, p. 253502, 2010. 

Chapter 5


1.K. Kahng and S. Sze, “A floating gate and its application to memory devices,” IEEE Trans. Electron Devices, vol. 14, pp. 1248-1253, 1997.
2.B. De Salvo, C. Gerardi, R. van Schaijk, “Performance and reliability features of advanced nonvolatile memories based on discrete traps,” IEEE Trans. Electron Devices and Materials reliability, vol. 4, pp. 377-389, 2004.
3.M. K. Cho and D. M. Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology,” IEEE Electron Device Lett., vol. 21, pp. 399-401, 2000.
4.Y. H. Lin, C. H. Chien, C. T. Lin, C. Y. Chang, and T. F. Lei, “High-performance nonvolatile HfO2 nanocrystal memory,” IEEE Electron Device Lett., vol. 26, pp. 154-156, 2005.
5.B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, A. Modelli, W. Inc, and C. Fremont, “Multilevel flash cells and their trade-offs,” in IEDM Tech. Dig., 1996, pp. 169-172.
6.S. M. Sze, K. K. Ng, “Physics of semiconductor devices” 3rd edition, Wiley, New Jersey ,2007
7.D. A. Baglee, and M. Smayling, ”The effects of write/erase cycling on data loss in
EEPROMs,” in IEDM Tech. Dig., 1985, pp. 624-626.
8.Y. H. Wu, M. L. Wu, Y. S. Lin, and J. R. Wu, “Electrical Characteristics of Thermal-SiON-gated Ge p-MOSFET formed on Si substrate,” IEEE Electron Device Lett., vol. 30, pp. 72-74, 2009.
9.Y. H. Wu, M. L. Wu, J. R. Wu, and Y. S. Lin, “Electrical characteristics of Ge p-MOSFETs formed on Si substrate with thermal SiON as gate dielectric,” in Proc. SSDM, 2008, pp. 762-763.
10.Y. Kamata, “High-k/Ge MOSFETs for future nanoelectronics,” Mater. Today., vol. 11, pp. 30-38, 2008.
11.D. Kuzum, A. J. Pethe, T. Krishnamohan, Y. Oshima, Y. Sun, J. P. McVittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, “Interface-engineered Ge (100) and (111), N- and P-FETs with high mobility,” in IEDM Tech. Dig., 2007, pp. 723-726.
12.S. Joshi, C. Krug, D. Heh, H. J. Na, H. R. Harris, J. W. Oh, P. D. Kirsch, P. Majhi, B. H. Lee, H. H. Tseng, R. Jammy, J. C. Lee, and S. K. Banerjee, “Improved Ge surface passivation with ultrathin SiOX enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack,” IEEE Electron Device Lett., vol. 28, pp. 308-311, 2007.
13.D. S. Yu, A. Chin, C. C. Liao, C. F. Lee, C. F. Cheng, M. F. Li, W. J. Yoo, and S. P. McAlister, “Three-dimensional metal gate-high-k-GOI CMOSFETs on 1-poly-6-metal 0.18-μm Si devices,” IEEE Electron Device Lett., vol. 26, pp. 118-120, 2005.
14.D. L. Kencke, X. Wang, Q. Ouyang, S. Mudanai, A. Tasch, and S. K. Banerjee, “Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability,” in Simulation of Semiconductor Process and Devices., 2000, pp. 151-154.
15.C. C. Wang, K. C. Chang-Liao, C. Y. Lu, and T. K. Wang, “Enhanced band-to-band-tunneling-induced hot-electron injection in p-channel flash by band-gap offset modification,” IEEE Electron Device Lett., vol. 27, pp. 749-751, 2006.
16.S. C. Wolfson and F. D. Ho, “Transient simulation to analyze flash memory erase improvements due to Germanium content in the substrate,” IEEE Trans. Electron Devices, vol. 57, pp. 2499-2503, 2010.
17.Y. H. Wu, J. R. Wu, and M. L. Wu, “Thermal gate SiO2 for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate,” Appl. Phys. Lett., vol. 91, p. 093503, 2007.
18.Y. H. Wu, J. R. Wu, Y. S. Lin, and M. L. Wu, “Thermal SiO2 gated Ge metal-oxide-semiconductor capacitor on Si substrate formed by thin amorphous Ge oxidation and thermal annealing,” Appl. Phys. Lett., vol. 93, p. 083506, 2008.
19.Y. H. Wu, W. J. Chen, A. Chin, and C. Tsai, “The effect of native oxide on epitaxial SiGe from deposited amorphous Ge on Si,” Appl. Phys. Lett., vol. 74, pp. 528-530, 1999.
20.D. N. Kouvatsos, V. L. Sougleridis, and A. G. Nassiopoulou, “Charging effects in silicon nanocrystals within SiO2 layers, fabricated by chemical vapor deposition, oxidation, and annealing,” Appl. Phys. Lett., vol. 82, pp. 397-399, 2003.
21.T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze, “Electron charging and discharging effects of tungsten nanocrystals embedded in silicon dioxide for low-voltage nonvolatile memory technology,” Electrochem. Solid-State. Lett., vol. 8, pp. G-71-G73, 2005.
22.M. Perego, G. Scarel, and M. Fanciulli, “Fabrication of GeO2 layers using a divalent Ge precursor,” Appl. Phys. Lett., vol. 90, p. 162115, 2007.
23.B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. D. Meyer, “VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices,” IEEE Electron Device Lett., vol. 24, pp. 99-101, 2003.
24.C. Sandhya, U. Ganguly, K. K. Singh, P. K. Singh, C. Olsen, S. M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, “Nitride engineering and the effect of interfaces on charge trap flash performance and reliability,” in Reliability Phjys. Symp. Tech. Dig., 2008, pp. 406-411.
25.C. H. Lai, A. Chin, H. L. Kao, K. M. Chen, M. Hong, J. Kwo, and C. C. Chi, “Very low voltage SiO2/HfON/HfAlO/TaN memory with fast speed and good retention,” in VLSI Symp. Tech. Dig., 2006, pp. 44-45.
26.C. Gerardi, S. Lombardo, G. Ammendola, G. Costa, V. Ancarani, D. Mello, S. Giuffrida, and M. C. Plantamura, “Study of nanocrystal memory integration in a flash-like NOR device,” Microelectron. Reliab., vol. 47, pp. 593-597, 2007. 

Chapter 6


1.A. I. Kingon, J. P. Maria, and S. K. Streiffer, “Alternative dielectrics to silicon dioxide for memory and logic devices,” Nature., vol. 406, pp. 1032-1038, 2000.
2.A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. Mcintyre, P. Mceuen, M. Lundstrom, and H. Dai, “High-k dielectrics for advanced carbon-nanotube transistors and logic gates,” Nat. Mater., vol. 1, pp. 241-246, 2002.
3.Y. Aoki and T. Kunitake, “Solution-based fabrication of high-k gate dielectrics for next-generation metal-oxide semiconductor transistors,” Adv. Mater., vol. 16, pp. 118-123, 2004.
4.J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, “Ge/Si nanowire heterostructures as high-performance field-effect transistors,” Nature., vol. 441, pp. 489-493, 2006.
5.L. Liao, J. Bai, Y. C. Lin, Y. Qu, Y. Huang, and X. Duan, “High-performance top-gated graphene-nanoribbon transistors using zirconium oxide nanowires as high-k dielectric-constant gate dielectrics,” Adv. Mater., vol. 22, pp. 1941-1945, 2010.
6.M. Zirkl, A. Haase, A. Fian, H. Scho‥n, C. Sommer, G. Jakopic, G. Leising, B. Stadlober, I. Graz, N. Gaar, R. Schwo‥diauer, S. Bauer-Gogonea, and S. Bauer, “Low-voltage organic thin-film transistors with high-k nanocomposite gate dielectrics for flexible electronics and optothermal sensors,” Adv. Mater., vol. 19, pp. 2241-2245, 2007.
7.A. Chin, C. C. Laio, C. Chen, K. C. Chiang, D. S. Yu, W. J. Yoo, G. S. Samudra, T. Wang, I. J. Hsieh, S. P. McAlister, and C. C. Chi, “Low voltage high speed SiO2/AlGaN/AlLaO3/TaN memory with good retention,” in IEDM Tech. Dig., 2005, pp. 158-161.
8.C. H. Lai, A. Chin, H. L. Kao, K. M. Chen, M. Hong, J. Kwo, and C. C. Chi, “Very low voltage SiO2/HfON/HfAlO/TaN memory with fast speed and good retention,” in VLSI Symp. Tech. Dig., 2006, pp. 44-45.
9.K. H. Kuesters, M. F. Beug, U. Schroeder, N. Nagel, U. Bewersdorff, G. Dallmann, S. Jakschik, R. Knoefler, S. Kudelka, C. Ludwig, D. Manger, W. Mueller, and A. Tilke, “New materials in memory development sub 50 nm: trends in flash and DRAM,” Adv. Mater., vol. 11, pp. 241-248, 2009.
10.H. J. Yang, C. F. Cheng, W. B. Chen, S. H. Lin, F. S. Yeh, S. P. McAlister, and A. Chin, “Comparison of MONOS memory device integrity when using Hf1−x−yNxOy trapping layers with different N compositions,” IEEE Trans. Electron Devices, vol. 55, pp. 1417-1423, 2008.
11.H. J. Yang, A. Chin, S. H. Lin, F. S. Yeh, and S. P. McAlister, “Improved high temperature retention for charge-trapping memory by using double quantum barriers,” IEEE Electron Device Lett., vol. 29, pp. 386-388, 2008.
12.P. H. Tsai, K. S. C. Liao, C. Y. Liu, T. K. Wang, P. J. Tzeng, C. H. Lin, and M. J. Tsai, “Novel SONOS-type nonvolatile memory device with optimal Al doping in HfAlO charge-trapping layer,” IEEE Electron Device Lett., vol. 29, pp. 265-268, 2008.
13.X. Zhao, and D. Vanderbilt, “Phonons and lattice dielectric properties of zirconia,” Phys. Rev. B., vol. 65, p. 075105, 2006.
14.D. Fischer, and A. Kersch “The effect of dopants on the dielectric constant of HfO2 and ZrO2 from first principles,” Appl. Phys. Lett., vol. 92, p. 012908, 2008.
15.Y. H. Wu, L. L. Chen, Y. S. Lin, M. Y. Li, and H. C. Wu, “Nitrided tetragonal as the charge-trapping layer for nonvolatile memory application,” IEEE Electron Device Lett., vol. 30, pp. 1290-1292, 2009.
16.Y. H. Wu, J. R. Wu, M. L. Wu, L. L. Chen, and Y. S. Lin, “Ge-based Silicon-oxide-nitride-oxide-silicon-type nonvolatile memory formed on Si substrate,” J. Electrochem. Soc., vol. 156, p. H944, 2009.
17.G. M. Rignanese, “Dielectric properties of crystalline and amorphous transition metal oxides and silicates as potential high-k candidates: the contribution of density-functional theory,” J. Phys. Condens. Matter., vol. 17, p. R357, 2005.
18.J. Mu‥ller, T. S. Bo‥scke, U. Schro‥der, M. Reinicke, L. Oberbeck, D. Zhou, W. Weinreich, P. Ku‥cher, M. Lemberger, and L. Frey, “Improved manufacturability of ZrO2 MIM capacitors by process stabilizing HfO2 addition,” Microeleltronic Eng., vol. 86, pp. 1818-1821, 2009.
19.Y. H. Wu, W. J. Chen, A. Chin, and C. Tsai, “The effect of native oxide on epitaxial SiGe from deposited amorphous Ge on Si,” Appl. Phys. Lett., vol. 74, pp. 528-530, 1999.
20.Y. H. Wu, J. R. Wu, and M. L. Wu, “Thermal gate SiO2 for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate,” Appl. Phys. Lett., vol. 91, p. 093503, 2007.
21.Y. H. Wu, M. L. Wu, Y. S. Lin, and J. R. Wu, “Electrical characteristics of thermal-SiON-gated Ge p-MOSFET formed on Si substrate,” IEEE Electron Device Lett., vol. 30, pp. 72-74, 2009.
22.Y. H. Wu, M. L. Wu, J. R. Wu, and Y. S. Lin, “Electrical characteristics of Ge MOS device on Si substrate with thermal SiON as gate dielectric,” Microeleltronic Eng., vol. 87, pp. 2423-2428, 2010.
23.M. Chun, M. J. Moon, J. Park, and Y. C. Kang, “Physical and chemical investigation of substrate temperature dependence of zirconium oxide films on Si (100),” Bill. Korean Chem. Soc., vol. 30, pp. 2729-2734, 2009.
24.N. A. Tabet, M. A. Salim, and A. L. Al-Oteibi, “XPS study of the growth kinetics of thin films obtained by thermal oxidation of germanium substrates,” J. Electron Spectrosc. Relat. Phenom., vol. 101-103, pp. 233-238, 1999.
25.D. Kuzum, T. Krishnamohan, A. J. Pethe, A. K. Okyay, Y. Oshima, Y. Sun, J. P. McVittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, “Ge-interface engineering with ozone oxidation for low interface-state density,” IEEE Electron Device Lett., vol. 29, pp. 328-330, 2008.
26.E. H. Nicollian and J. R. Brews, MOS Physics and Technology, pp. 196-197, John Wiley & Sons, New York (1982).
27.D. N. Kouvatsos, V. Ioannou-Sougleridis, and A. G. Nassiopoulou, “Charging effects in silicon nanocrystals within SiO2 layers, fabricated by chemical vapor deposition, oxidation, and annealing,” Appl. Phys. Lett., vol. 82, pp. 397-399, 2003.
28.P. Normand, E. Kapetanakis, P. Dimitrakis, D. Tsoukalas, K. Beltsios, N. Cherkashin, C. Bonafos, G. Benassayag, H. Coffin, A. Claverie, and M. Ameen, “Effect of annealing environment on the memory properties of thin oxides with embedded Si nanocrystals obtained by low-energy ion-beam synthesis,” Appl. Phys. Lett., vol. 83, pp. 168-170, 2003.
29.C. C. Wang, Y. K. Chiou, C. H. Chang, J. Y. Tseng, L. J. Wu, C. Y. Chen, and T.B. Wu, “Memory characteristics of Au nanocrystals embedded in metal-oxide-semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide,” J. Phys. D: Appl. Phys., vol. 40, pp. 1673-1677, 2007.
30.D. K. Chen, F. E. Mamouni, X. J. Zhou, R. D. Schrimpf, D. M. Fleetwood, K. F. Galloway, S. Lee, H. Seo, G. Lucovsky, B. Jun, and J. D. Cressler, “Total dose and bias temperature stress effects for HfSiON on Si MOS capacitors,” IEEE Trans. Nucl. Sci., vol. 54, pp. 1931-1937, 2007.
31.J. Robertson, “High dielectric constant oxides,” Eur. Phys. J. Appl. Phys., vol. 28, pp. 265-291, 2004.
32.A. K. Stamper, D. W. Greve, and T. E. Schiesinger, “Deposition of textured yttria‐stabilized ZrO2 films on oxidized silicon,” J. Appl. Phys., vol. 70, pp. 2046-2051, 1991.
33.K. S. Seol, S. J. Choi, J. Y. Choi, E. J. Jang, B. K. Kim, S. J. Park, D. G. Cha, I. Y. Song, J. B. Park, Y. Park, and S. H. Choi, “Pd-nanocrystal-based nonvolatile memory structures with asymmetric SiO2/HfO2 tunnel barrier,” Appl. Phys. Lett., vol. 89, p. 083109, 2006.
34.Y. S. Lo, K. C. Liu, J. Y. Wu, C. H. Hou, and T. B. Wu, “Bandgap engineering of tunnel oxide with multistacked layers of Al2O3/HfO2/SiO2 for Au-nanocrystal memory application,” Appl. Phys. Lett., vol. 93, p. 132907, 2008.
35.S. Shim, F. C. Yeh, X. W. Wang, and T. P. Ma, “SONOS-type flash memory cell with metal structure for low-voltage high-speed program/erase operation,” IEEE Electron Device Lett., vol. 29, pp. 512-514, 2008.
36.A. S. Foster, V. B. Sulimov, F. L. Gejo, A. L. Shluger, and R. M. Nieminen, “Structure and electrical levels of point defects in monoclinic zirconia,” Phys. Rev. B., vol. 64, p. 224108, 2001.
37.J. Fu, K. D. Buddharaju, S. H. G. Teo, C. Zhu, M. B. Yu, N. Singh, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “Trap layer engineered gate-all-around vertically stacked twin Si-nanowire nonvolatile memory,” in IEDM Tech. Dig., 2007, pp. 79-82.
38.R. Ohba, Y. Mitani, N. Sugiyama, and S. Fujita, “10 nm bulk-planar SONOS-type memory with double tunnel junction and sub-10 nm scaling utilizing source to drain direct tunnel sub-threshold,” in IEDM Tech. Dig., 2008, pp. 15-17.
39.P. Blomme, M. Rosmeulen, A. Cacciato, M. Kostermans, C. Vrancken, S. V. Aerde, T. Schram, I. Debusschere, M. Jurczak, and J. V. Houdt, “Novel dual layer floating gate structure as enabler of fully planar flash memory,” in VLSI Symp. Tech. Dig., 2010, pp. 129-130. 


Chapter 7


1.N. Xu, L. Liu, X. Sun, X. Liu, D. Han, Y. Wang, R. Han, J. Kang, and B. Yu, “Characteristics and mechanism of conduction/set process in TiN/ZnO/Pt resistance switching random-access memories,” Appl. Phys. Lett., vol. 92, p. 232112, 2008.
2.C. H. Cheng, A. Chin and F. S. Yeh, “High performance ultra-low energy RRAM with good retention and endurance,” in IEDM Tech. Dig., 2010, pp. 448-451.
3.H. Kim, P. C. Mclntyre, C. O. Chui, and K. C. Saraswat, “Engineering chemically abrupt high-k metal oxide/silicon interfaces using an oxygen-gettering metal overlayer,” J. Appl. Phys., vol. 96, pp. 3467-3472. 2004.
4.Y. W. Chang, Y. C. Lai, T. B. Wu, S. F. Wang, F. Chen, and M. J. Tsai, “Unipolar resistive switching characteristics of ZnO thin films for nonvolatile memory applications,” Appl. Phys. Lett., vol. 92, p. 022110, 2008.
5.J. S. Choi, J. S. Kim, I. R. Hwang, S. H. Hong, S. H. Jeon, S. O. Kang, B. H. Park, D. C. Kim, M. J. Lee, and S. Seo, “Different resistance switching behaviors of NiO thin films deposited on Pt and SrRuO3 electrodes",” Appl. Phys. Lett., vol. 95, p. 022109, 2009.
6.S. S. Sheu, P. C. Chiang, W. P. Lin, H. Y. Lee, P. S. Chen, Y. S. Chen, T. Y. Wu, F. T. Chen, K. L. Su, M. J. Kao, K. H. Cheng, and M. J. Tsai, “A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme,” in VLSI Circuit. Tech. Dig., 2009, pp. 82-83.
7.M. Wang, W. J. Luo, Y. L. Wang, L. M. Yang, W. Zhu, P. Zhou, J. H. Yang, X. G. Gong, Y. Y. Lin, R. Huang, S. Song, Q. T. Zhou, H. M. Wu, J. G. Wu, and M. H. Chi, “A novel CuxSiyO resistive memory in logic technology with excellent data retention and resistance distribution for embedded applications,” in VLSI Symp. Tech. Dig., 2010, pp. 89-90.
8.S. S. Sheu, K. H. Cheng, M. F. Chang, P. C. Chiang, W. P. Lin, H. Y. Lee, P. S. Chen, Y. S. Chen, T. Y. Wu, F. T. Chen, K. L. Su, M. J. Kao, and M. J. Tsai, “Fast-write resistive RAM (RRAM) for embedded applications,” IEEE Design & Test of Computers., vol. 28, pp. 64-71, 2011.
9.C. H. Wang, Y. H. Tsai, K. C. Lin, M. F. Chang, Y. C. King, C. J. Lin, S. S. Sheu, Y. S. Chen, H. Y. Lee, F. T. Chen, and M. J. Tsai, “Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process,” in IEDM Tech. Dig., 2010, pp. 664-667.
10.A. Chen, S. Haddad, Y. C. Wu, T. N. Fang, S. Kaza, and Z. Lan, “Erasing characteristics of Cu2O metal-insulator-metal resistive switching memory,” Appl. Phys. Lett., vol. 92, p. 013503, 2008.
11.H. Lv, M. Wang, H. Wan, Y. Song, W. Luo, P. Zhou, T. Tang, Y. Lin, R. Huang, S. Song, J. G. Wu, H. M. Wu, and M. H. Chi, “Endurance enhancement of Cu-oxide based resistive switching memory with Al top electrode,” Appl. Phys. Lett., vol. 94, p. 213502, 2009.
12.K. P. Chang, W. C. Chien, Y. C. Chen, E. K. Lai, S. C. Tsai, S. H. Hsieh, Y. D. Yao, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Low-voltage and fast-speed forming process of tungsten oxide resistive memory,” in Proc. SSDM, 2008, pp. 1168-1169.
13.R. Waser and M. Aono, “Nanoionics-based resistive switching memories,” Nat. Mater., vol. 6, pp. 833-840, 2007.
14.K. Terabe, T. Hasegawa, T. Nakayama, and M. Aono, “Quantized conductance atomic switch,” Nat., vol. 433, pp. 47-50, 2004.
15.M. Fujimoto, H. Koyama, M. Konagai, Y. Hosoi, K. Ishihara, S. Ohnishi, and N. Awaya, “TiO2 anatase nanolayer on TiN thin film exhibiting high speed bipolar resistive switching,” Appl. Phys. Lett., vol. 89, p. 223509, 2006.
16.C. Y. Lin, C. Y. Wu, C. Y. Wu, T. C. Lee, F. L. Yang, C. Hu, and T. Y. Tseng, “Effect of top electrode material on resistive switching properties of ZrO2 film memory devices,” IEEE Electron Device Lett., vol. 28, pp. 366-368, 2007.
17.Y. H. Wu, J. R. Wu, and M. L. Wu, “Thermal gate SiO2 for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate,” Appl. Phys. Lett., vol. 91, p. 093503, 2007.
18.Y. H. Wu, M. L. Wu, J. R. Wu, and L. L. Chen, “Ge-stabilized tetragonal ZrO2 as gate dielectric for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate,” Appl. Phys. Lett., vol. 97, p. 043503, 2010.
19.C. O. Chui, H. Kim, P. C. McIntyre, K. C. Saraswat, “A germanium NMOSFET process integrating metal gate and improved hi-k dielectrics,” in IEDM Tech. Dig., 2003, pp. 437-440.
20.R. Xie, M. Yu, M. Y. Lai, L. Chan, and C. Zhu, “High-k gate stack on germanium substrate with fluorine incorporation,” Appl. Phys. Lett., vol. 92, p. 163505, 2008.
21.Y. T. Chen, H. Zhao, Y. Wang, F. Xue, F. Zhou, and J. C. Lee, “Effects of fluorine incorporation into HfO2 gate dielectrics on InP and In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors,” Appl. Phys. Lett., vol. 96, p. 253502, 2010.
22.J. J. Yang, M. D. Pickett, X. Li, D. A. Ohlberg, D. R. Stewart, and R. S. Williams, “Memristive switching mechanism for metal/oxide/metal nanodevices,” Nat. Nanotechnol., vol. 3, pp. 429-433, 2008
23.B. Kaczer, B. De Jaeger, G. Nicholas, K. Martens, R. Degraeve, M. Houssa, G. Pourtois, F. Leys, M. Meuris, and G. Groeseneken, “Electrical and reliability characterization of metal-gate/HfO2/Ge FET’s with Si passivation,” Microelectron. Eng., vol. 84, pp. 2067-2070, 2007. 

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊