本論文為實現快速主成分分析之硬體，提出三種GHA的硬體架構，分別為達成高速計算及最少的硬體資源消耗為目的。在高速計算的架構，所有主成分值計算與突觸權重值之更新，皆使用專屬的電路作並行之運算。對於高維度訓練資料之適用架構，以所有主成分值計算共用一個主成分計算電路輪流完成計算，並將訓練資料區塊化方式逐步更新每個神經元的突觸權重值。所有實現的硬體架構訓練取得之權重向量，應用在紋理的分類。

This dissertation proposes three types of GHA architectures, achieving the aims of high speed computation and low area costs, for fast principal component analysis. In the architecture with high speed computation, all principal components computation and synaptic weight vectors updating are operated concurrently in individual dedicated circuits. In the architectures with high-dimensional training vector, all principal components can be sequentially computed by a single circuit. Meanwhile, each synaptic weight vector is updated block by block in fixed number of synaptic weight updating modules. To demonstrate the effectiveness of the proposed architectures, texture classification will be adopted.

中文摘要 i
Abstract ii
誌 謝 iii
Contents v
List of Figures vii
List of Tables xi
Chapter 1 Introduction 1
1.1 Introduction and Literature Review 1
1.2 Overview of Proposed Architectures 4
1.3 Organization of the Dissertation 7
Chapter 2 Neural Network Model 8
2.1 Principal Components Analysis 8
2.2 Hebbian-Based Maximum Eigenfilter 11
2.3 Generalized Hebbian Algorithm 15
Chapter 3 Basic GHA Architectures 17
3.1 The Direct GHA Implementation 17
3.1.1 The Basic Building Blocks of the GHA Architecture 18
3.1.2 The Direct Implementation 20
3.1.3 The Direct Implementation of PCC Unit 22
3.1.4 Reducing the Area Costs for SWU and PCC Implementations 23
3.2 GHA Architecture I 26
3.2.1 Definition of Area Complexities and Latency of the Basic GHA 26
3.2.2 Synaptic Weight Updating Unit of Architecture I 27
3.2.3 Principal Components Computing Unit of Architecture I 30
3.2.4 Memory Unit of Architecture I 34
3.2.5 Analysis of the Area Complexities and Latency of Architecture I 35
3.3 Experimental Results 37
3.3.1 SOPC-Based GHA Training Platform 37
3.3.2 Texture Classification Application System 38
3.3.3 Experimental Results 40
Chapter 4 GHA Architecture II 47
4.1 Architecture II 47
4.1.1 SWU Unit 47
4.1.2 Memory Unit 54
4.1.3 PCC Unit 56
4.2 Experimental Results 58
Chapter 5 GHA Architecture III 65
5.1 Architecture III 65
5.1.1 SWU Unit 65
5.1.2 PCC Unit 69
5.1.3 Memory Unit 71
5.2 Experimental Results 78
Chapter 6 Conclusion and Future Works 88
6.1 Concluding Remarks 88
6.2 Future Works 90
Bibliography 91
Publication List 94

[Alp10] E. Alpaydin, Introduction to Machine Learning, 2nd ed., MIT Press, Massachusetts, USA, 2010.
[Bra10] Ignacio Bravo, Manuel Mazo, José L. Lázaro, Alfredo Gardel, Pedro Jiménez and Daniel Pizarro “An Intelligent Architecture Based on FPGA Designed to Detect Moving Objects by Using Principal Component Analysis,” Sensors, Vol. 10, pp. 9232 - 9251, 2010.
[Broda] Brodatz Textures Collection, http://www.ux.uis.no/~tranden/brodatz.html
[Boo01] W. Boonkumklao, Y. Miyanaga, and K. Dejhan, “Flexible PCA architecture realized on FPGA,” International Symposium on Communications and Information Technologies, pp.590 - 593, 2001.
[Car07] Gonzalo Carvajal, Waldo Valenzuela, and Miguel Figueroa, “Subspace-Based Face Recognition in Analog VLSI,” Advances in Neural Information Processing Systems, Vol. 20, MIT Press, Cambridge, pp. 225–232, 2007.
[Car09] Gonzalo Carvajal, Waldo Valenzuela, and Miguel Figueroa, “Image recognition in analog VLSI with on-chip learning”, Lecture Notes in Computer Science, Vol. 5768, pp. 428 - 438, 2009.
[Che08] Tung-Chien Chen, Wentai Liu, and Liang-Gee Chen, “VLSI architecture of leading eigenvector generation for on-chip principal component analysis spike sorting system,” Proceedings of the IEEE Engineering in Medicine and Biology Society Conference, Vancouver, pp. 3192-3195, 2008.
[Che09] Dake Chen and Han Jiu-qiang, “An FPGA-based Face Recognition Using Combined 5/3 DWT with PCA Methods,” Journal of Communication and Computer, Vol. 6, 2009.
[Dav12] David C. Lay and Eric Stade, Linear Algebra and Its Applications, 4th ed., Addison Wesley, 2012.
[Dag06] Issam Dagher and Rabih Nachar, “Face recognition using IPCA-ICA algorithm,” IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol. 28, pp. 996-1000, 2006.
[Dia96] K. I. Diamantaras and S. Y. Kung, Principal Component Neural Networks Theory and Applications, 1st ed., Wiley-Interscience, 1996.
[Got06] Rajkiran Gottumukkal, Hau T. Ngo, and Vijayan K. Asari, “Multi-lane architecture for eigenface based real-time face recognition,”Microprocessors and Microsystems, Vol. 30, pp. 216 - 224, 2006.
[Hay09] Simon, Haykin, Neural Networks and Learning Machines, 3rd ed., Pearson, 2009.
[Jol02] I. T. Jolliffe, Principal Component Analysis, 2nd ed., Springer-Verlag, New York, 2002.
[Kim05] Kwang In Kim, Matthias O. Franz, and Bernhard Schö lkopf, “Iterative kernel principal component analysis for image modeling,” IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol. 27, pp. 1351 - 1366, 2005.
[Lin11] Shiow-Jyu Lin, Yi-Tsan Hung, and Wen-Jyi Hwang, “Efficient hardware architecture based on generalized Hebbian algorithm for texture classification,” Neurocomputing, Vol. 74, pp. 3248 - 3256, 2011.
[Ngo05] Hau T. Ngo, Rajkiran Gottumukkal, and Vijayan K. Asari, “A flexible and efficient hardware architecture for real-time face recognition based on eigenface,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 280 - 281, 2005.
[Pav07] A. Pavan Kumar, V. Kamakoti, and Sukhendu Das, ” System-on-programmable-chip implementation for on-line face recognition,” Pattern Recognition Letters, Vol. 28, pp. 342 - 349, 2007.
[Row98] Sam Roweis,”EM algorithms for PCA and SPCA,” Advances in Neural Information Processing Systems, Vol. 10, pp. 626 - 632, 1998.
[Saj08] I. Sajid, M.M. Ahmed, and I. Taj, “ Design and Implementation of a Face Recognition System Using Fast PCA,” International Symposium on Computer Science and its Applications, pp. 126 - 130, 2008.
[San89] Terence D. Sanger, “Optimal Unsupervised Learning in a Single-Layer Linear Feedforward Neural Network,” Neural Networks, Vol. 2, pp. 459 - 473, 1989.
[Sha07] Alok Sharma and Kuldip K. Paliwal, “Fast principal component analysis using fixed-point algorithm,” Pattern Recognition Letters, Vol. 28, pp. 1151 - 1155, 2007.
[Sud08] A.R. Mohan, N. Sudha, and P.K. Meher, “An embedded face recognition system on a VLSI array architecture and its FPGA implementation,” Proceedings of the IEEE Conference on Industrial Electronics, pp. 2432 - 2437, 2008.
[Sud11] A.R. Mohan, N. Sudha, and P.K. Meher, “A Self-Configurable Systolic Architecture for Face Recognition System Based on Principal Component Neural Network,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 21, pp.1071-1084, 2011.