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研究生:謝正恩
研究生(外文):Cheng-En Hsieh
論文名稱:用於逐次逼近式類比數位轉換器之高效能浮動開關電容技術設計
論文名稱(外文):A High Energy-Efficiency SAR ADC with Floating Capacitor Switching Technique
指導教授:郭建宏郭建宏引用關係
指導教授(外文):Chien-Hung Kuo
學位類別:碩士
校院名稱:國立臺灣師範大學
系所名稱:應用電子科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:100
語文別:中文
論文頁數:106
中文關鍵詞:類比數位轉換器逐次逼近暫存器電容式數位類比轉換電路浮動開關電容技術品質因數FOM
外文關鍵詞:Analog-to-digital convertersuccessive approximation registercapacitive DAC arrayfloating capacitor switching (FCS)figure of merit (FOM)
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積體電路設計在現今製程技術的演進下,已開啟奈米時代。而製程精度的提升除了降低電路佈局的面積,驅使電路運作的電源電壓因而縮小,使得高效能與低功率的電路設計不斷產出。隨著可攜式電子產品高需求的帶動下,效能佳是現今產品發表的最基本門檻,反倒是輕薄短小以及電池的長時效性要求,逐漸成為電路設計之主流;特別是應用在人體或生物上的植入性醫學晶片,為了能達到永久使用不更換的最大目標,低功率對晶片的設計上,更是第一必備要件。在眾多的類比數位轉換器中,逐次逼近式類比數位轉換器(successive approximation register analog-to-digital converter, SAR ADC)最符合低功率的條件,在於其大部分的電路元件為數位邏輯所構成,以及每筆取樣資料的轉換過程中,僅需一顆比較器即可實現,這都大幅地縮減資料轉換所消耗的能源。然而,在製程技術逐年提升的影響下,具備較多數位電路的SAR ADC開始嶄露頭角,除了維持低功率的特色,也朝高速的電路設計方案邁進。
在本論文中,提出了浮動開關電容(floating capacitor switching, FCS)技術來降低電容式DAC的能量損耗,相較於傳統切換技術之DAC架構,所提出方法可有效的節省97.66%的平均能量損失。另外,在供應電壓0.9-V的操作下,結合FCS架構的電容切換方式,再提出了部分式浮動開關電容技術之差動SAR ADC,以及雙部分式浮動開關電容技術之單端SAR ADC的電路實現架構,並採用TSMC 0.18-μm 1P6M的標準製程完成,在奈式取樣頻寬的規格下,可達到的品質因數FOM值分別為21.7-fJ/conversion-step以及46.2-fJ/conversion-step。

With the development of modern CMOS fabrication, the integrated circuits had entered into the nanoscale. Smaller area and lower voltage design might be come true by the advanced processing. Hence, low-power with high-performance circuits had been presented constantly. Nowadays, the mainstream products trend of portable electronic devices, greatly chip performance is replaced by smaller, cheaper and long standby. In particular, low-power was an essential condition on the human body or biological implantable chip applications. All of analog-to-digital converter (ADC) types, successive approximation register (SAR) is appropriate for the low-power design by their much more digital circuits. Besides, the power dissipation can be significantly reduced by only one comparator which is needed to complete whole sampling data during each conversion phase. In addition, some of high speed circuits using SAR approach can be accomplished recently with the advanced process.
In this thesis, seeking the comparison between a floating capacitor switching (FCS) scheme is proposed to reduce the energy consumption and conventional DAC approach, the proposed scheme can achieve 97.66% less average switching energy. Furthermore, the actuality architectures are realized by the partial FCS scheme based differential SAR ADC and double partial FCS scheme based single-ended SAR ADC at a 0.9-V supply voltage. Both of them were fabricated in the TSMC 0.18-μm 1P6M process technology. The presented SAR ADCs can achieve 21.7-fJ/conversion-step and 46.2-fJ/conversion-step figure of merit (FOM) in the Nyquist bandwidth, respectively.

中文摘要 I
英文摘要 III
誌  謝 V
目  錄 VII
圖 目 錄 XI
表 目 錄 XV
第一章 緒論 1
  1.1 研究背景與動機 1
  1.2 混合信號系統概述 3
  1.3 論文架構與研究方法 4
第二章 類比數位轉換器概論 5
  2.1 前言 5
  2.2 取樣定理 5
  2.3 量化器 7
   2.3.1 二進位量化器 7
   2.3.2 多位元量化器 8
    1. Mid-rise量化器 9
    2. Mid-tread量化器 10
    3. 多位元量化器的非理想特性 10
   2.3.3 量化誤差 11
  2.4 效能規格指標 13
   2.4.1 信號雜訊比 13
   2.4.2 信號雜訊失真比 14
   2.4.3 動態範圍 14
   2.4.4 無雜散動態範圍 15
   2.4.5 非線性誤差 15
   2.4.6 品質因數 15
  2.5 逐次逼近式類比數位轉換器 16
   2.5.1 逐次逼近想法實例 17
   2.5.2 二位元搜尋演算法 17
第三章 低電壓操作之SAR ADC電路元件 19
  3.1 前言 19
  3.2 取樣保持電路及開關元件 20
   3.2.1 MOS開關 21
   3.2.2 互補式傳輸閘開關 22
   3.2.3 低臨界電壓技術 23
   3.2.4 時脈倍壓電路 23
   3.2.5 靴帶式開關 25
   3.2.6 以靴帶式開關實現之取樣保持電路 25
  3.3 比較器電路 28
   3.3.1 比較器的非理想效應 28
   3.3.2 軌對軌比較器 29
   3.3.3 動態比較器 31
  3.4 逐次逼近暫存器 32
   3.4.1 Non-redundant SAR工作程序 33
   3.4.2 Non-redundant SAR電路實現 34
   3.4.3 單相位時序正反器 36
  3.5 數位類比轉換器 37
   3.5.1 電阻式數位類比轉換器 37
   3.5.2 電流式數位類比轉換器 39
   3.5.3 電容式數位類比轉換器 39
  3.6 時脈產生器 41
第四章 高效能浮動開關電容式SAR ADC 43
  4.1 開關電容能量損耗 43
  4.2 電荷重新分佈原理 43
  4.3 傳統SAR ADC架構 44
   4.3.1 取樣保持狀態之能量分析 45
   4.3.2 電荷重新分佈之能量分析 47
   4.3.3 傳統SAR ADC架構能量損耗 51
  4.4 浮動開關電容式SAR ADC架構 52
   4.4.1 取樣保持狀態之能量分析 54
   4.4.2 電荷重新分佈G2之能量分析 55
   4.4.3 電荷重新分佈G3與G4之能量分析 58
   4.4.4 電荷重新分佈G5之能量分析 61
   4.4.5 浮動開關電容式SAR ADC架構能量損耗 66
  4.5 總結 67
第五章 浮動開關電容式SAR ADC實現 69
  5.1 前言 69
  5.2 開關斷接之寄生電容考量 69
  5.3 部分式浮動開關電容技術之差動SAR ADC架構 71
   5.3.1 電路設計與模擬 73
   5.3.2 電路佈局與實現 76
   5.3.3 晶片量測環境 77
    1. 輸入信號與終端介面 78
    2. LM317電壓調節電路 79
    3. OP27電壓調節電路 80
    4. 濾波槽電路 81
   5.3.4 量測結果 81
  5.4 雙部分式浮動開關電容技術之單端SAR ADC架構 83
   5.4.1 電路設計與模擬 86
   5.4.2 電路佈局與實現 88
   5.4.3 晶片量測環境 89
   5.4.4 量測結果 91
  5.5 總結 92
第六章 總結與未來展望 95
  6.1 總結 95
  6.2 未來展望 96
參 考 文 獻 99
作 者 簡 歷 103
學 術 成 就 105

[1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Companies, Inc., 2002.
[2] D. A. Johns and K. Martin, Analog CMOS Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
[3] R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Second Edition, John Wiley & Sons, Inc., 2008.
[4] K.-L. Lin, A. Kemna, and B. J. Hosticka, Modular low-power, high-speed CMOS analog-to-digital converter for embedded systems, Kluwer Academic Publishers, 2003.
[5] M. Keating and P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition, Kluwer Academic Publishers, 2001.
[6] J. McCreary and P. R. Gray, “A high-speed, all-MOS successive-approximation weighted capacitor A/D conversion technique,” IEEE Int. Solid-State Circuits Conf., Feb. 1975, pp. 38–39.
[7] S. Mortezapour and E. K. F. Lee, “A 1-V, 8-Bit successive approximation ADC in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 642–646, Apr. 2000.
[8] G. Promitzer, “12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1138–1143, Jul. 2001.
[9] M. D. Scott, B. E. Boser, and K. S. J. Pister, “An ultralow-energy ADC for smart dust,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1223–1229, Jul. 2003.
[10] T. Yoshida, M. Sasaki, and A. Iwata, “A 1-V supply successive approximation ADC with rail-to-rail input voltage range,” IEEE Int. Symp. Circuits Syst., May 2005, pp. 192–195.
[11] H. P. Le, J. Singh, L. Hiremath, V. Mallapur, and A. Stojcevski, “Ultra-low-power variable-resolution successive approximation ADC for biomedical application,” Electron. Lett., vol. 41, no. 11, May 2005.
[12] J. Sauerbery, T. Tille, D. S. Landsiedel, and R. Thews, “A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1662–1669, Dec. 2002.
[13] G.-C. Ahn, D.-Y. Chang, M. E. Brown, N. Ozaki, H. Youra, K. Hamashita, K. Takasuka, G. C. Temes, and U.-K. Moon, “A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2398–2407, Dec. 2005.
[14] J. Shen and P. Kinget, “A 0.5-V 8-bit 10-Msps pipelined ADC in 90-nm CMOS,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 202–203.
[15] M. Waltari and K. A. I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE J. Solid-State Circuits, vol. 36, no. 1, Jan. 2001.
[16] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1-μW successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261–1265, Jul. 2003.
[17] H.-C. Hong and G.-M. Lee, “A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161–2168, Oct. 2007.
[18] C.-H. Kuo and C.-E. Hsieh, “A high energy-efficiency SAR ADC based on partial floating capacitor switching technique,” IEEE Eur. Solid-State Circuits Conf., Sep. 2011, pp. 475–478.
[19] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” IEEE Int. Symp. Circuits Syst., May 2005, pp. 184–187.
[20] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007.
[21] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500-KS/s low power SAR ADC for bio-medical applications,” IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 228–231.
[22] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010.
[23] V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, no. 9, pp. 620–621, Apr. 2010.
[24] T. Anand, V. Chaturvedi, and B. Amrutur, “Energy efficient asymmetric binary search switching technique for SAR ADC,” Electron. Lett., vol. 46, no. 22, pp. 1487–1488, Oct. 2010.
[25] Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111–1121, Jun. 2010.
[26] C.-H. Kuo and C.-E. Hsieh, “Floating capacitor switching SAR ADC,” Electron. Lett., vol. 47, no. 13, pp. 742–743, Jun. 2011.
[27] M. Dessouky and A. Kaiser, “Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 349–355, Mar. 2001.
[28] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched op amp circuits,” Electron. Lett., vol. 35, no. 1, pp. 8–10, Jan. 1999.
[29] H. T. Russell and JR., “An improved successive-approximation register design for use in A/D converters,” IEEE Trans. Circuits Syst., vol. 25, no. 7, pp. 550–554, Jul. 1978.
[30] A. Rossi and G. Fucili, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, pp. 1055–1057, Jun. 1996.
[31] J. Yuan and C. Svensson, “New TSPC latches and flipflops minimizing delay and power,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1996, pp. 160–161.
[32] D. Schinkel, E. Mensink, E. Kiumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps setup+hold time,” IEEE Int. Solid State Circuits Conf., Feb. 2007, pp. 314–605.
[33] M. Elzakker, E. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC consuming 1.9-μW at 1-MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007–1015, May 2010.
[34] A. Nikoozadeh and B. Murmann, “An analysis of latch comparator offset due to load capacitor mismatch,” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 12, pp. 1398–1402, Dec. 2006.
[35] J. He, S. Zhan, D. Chen, and R. L. Geiger, “Analyses of static and dynamic random offset voltages in dynamic comparators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp. 911–919, Jul. 2009.
[36] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, 1999.
[37] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and J. Craninckx, “An 820-μW 9b 40-MS/s noise tolerant dynamic SAR ADC in 90-nm digital CMOS,” IEEE Int. Solid-State Circuits Conf., Feb. 2008, pp. 238–610.
[38] N. Verma and A. P. Chandrakasan, “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1196–1205, Jun. 2007.
[39] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB 1-V 3.8-μW 100-kS/s SAR ADC with time-domain comparator,” IEEE Int. Solid State Circuits Conf., Feb. 2008, pp. 245–247.
[40] W.-Y. Pang, C.-S. Wang, Y.-K. Chang, N.-K. Chou, and C.-K. Wang, “A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications,” IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 149–152.
[41] G. Yin, U-F. Chio, H.-G. Wei, S.-W. Sin, S.-P. U, R. P. Martins, and Z. Wang, “An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications,” IEEE Int. Conf. Electron. Circuits Syst., Dec. 2010, pp. 878–881.
[42] J.-H. Cheong, K.-L. Chan, P. B. Khannur, K.-T. Tiew, and M. Je, “A 400-nW 19.5-fJ/conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18-μm CMOS,” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 58, no. 7, pp. 407–411, Jul. 2011.

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