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研究生:林耀千
研究生(外文):Yao-Chian Lin
論文名稱:應用於無線通信之低相位雜訊電壓控制振盪器設計
論文名稱(外文):Design of Low Phase Noise Voltage-Controlled Oscillators for Wireless Communications
指導教授:葉美玲葉美玲引用關係張忠誠張忠誠引用關係
指導教授(外文):Mei-Ling YehChung-Cheng Chang
學位類別:博士
校院名稱:國立臺灣海洋大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:94
中文關鍵詞:電壓控制振盪器調諧範圍相位雜訊性能指標功率頻率調諧標準化
外文關鍵詞:voltage-controlled oscillatorstuning rangephase noisefigure-of-meritpower-frequency-tuning-normalized
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近年來,無線通信系統之研究有卓越的發展,目前對於應用於無線通信射頻前端積體電路系統,低相位雜訊、低功率以及高效能為主要的訴求,為了成功實現規格要求,則需要創新的電路設計。
本論文設計五顆不同頻段的電壓控制振盪器以應用於射頻前端積體電路系統,且達到低相位雜訊及高效能等特性,電路均使用TSMC 0.18 μm 1P6M CMOS製程技術設計。
設計寬調諧範圍及超低相位雜訊的4.27 GHz電壓控制振盪器,使用源極退化電容技術實現寬調諧範圍。 操作頻率為3.53~4.34 GHz,頻寬為810 MHz,量測相位雜訊在1 MHz偏移為 -131.2 dBc/Hz, 對應的性能指標(FOM)及功率頻率調諧標準化(PFTN)分別為 -191.6 dBc/Hz及3.3 dB,晶片面積0.469 mm2,核心電路消耗功率為16.5mW及供應電壓1.3V。
應用於OC-192 SONET全積體化CMOS LC 電壓控制振盪器,使用電容回授技術實現低雜訊性能。量測的可調諧範圍10.875~11.1 GHz,量測相位雜訊在1 MHz偏移為 -120.42 dBc/H及高性能指標為-189.5 dBc/Hz。輸出頻譜顯示振盪頻率在10.94 GHz的輸出功率為 -10.51dBm,核心電路消耗功率為15 mW及供應電壓1.8V。
應用於Ku-Band高效能、低相位雜訊及低消耗功率CMOS 15.57 GHz電壓控制振盪器設計,使用電容回授技術實現低雜訊與高性能的特性。量測相位雜訊在1 MHz偏移為 -116.6 dBc/Hz及優秀的性能指標 -192.66 dBc/Hz,可調諧範圍大約為290 MHz,消耗功率為6mW及晶片面積為0.377 mm2。
應用於K-Band低雜訊電壓控制振盪器設計,使用電容回授技術實現低雜訊。VCO的可調諧範圍20.817~20.266 GHz,量測相位雜訊在1 MHz偏移為 -115.57 dBc/Hz,對應的性能指標為 -190 dBc/Hz及晶片面積為0.377 mm 2。
應用於Ka-band 高效能低功率27 GHz CMOS 電壓控制振盪器設計,使用基板偏壓技術來改善VCO的功率消耗。可調諧範圍26.35~27.102 GHz及量測相位雜訊1 MHz偏移為 -106.2dBc/Hz,對應的性能指標為 -183.2 dBc/Hz及晶片面積為0.39 mm 2,振盪中心頻率在27.075 GHz的輸出功率為 -25.36 dBm。

In recent years, wireless communication research has experienced remarkable evolution. Low phase noise, low power, and high performance are the essential requirements for RF front-end integrated circuit system in wireless communication. In order to successfully meet the specification requirements, we need innovative circuit design.
We have designed five voltage-controlled oscillators (VCOs) operating at different frequency bands for the application to RF front-end integrated circuit system. These VCOs achieve low phase noise and high performance and are implemented using TSMC 0.18μm 1P6M CMOS process.
In the design of a wide tuning range and ultra low phase-noise 4.27 GHz VCO, we use source capacitive degeneration topology to obtain wide tuning range. The operation frequency is from 3.53 GHz to 4.34 GHz and the tuning range is 810 MHz. The measured phase noise is -131.2-dBc/Hz at 1 MHz offset. The corresponding figure-of-merit (FOM) and power-frequency-tuning-normalized (PFTN) factor are calculated to be -191.6 dBc/Hz and 3.3 dB, respectively. The chip size is 0.469 mm2. The core circuit consumes 16.5mW from a 1.3-V power supply.
A fully integrated CMOS LC VCO using capacitive feedback technology achieves low phase noise for OC-192 SONET applications. The measured tuning range is 10.875~11.1 GHz. The measured phase noise is -120.42 dBc/Hz at 1 MHz offset and the high FOM is -189.5 dBc/Hz. The output power is -10.51dBm at oscillator frequency of 10.94 GHz in output spectrum. The core circuit consumes power of 15 mW from a 1.8 V supply voltage.
In the application to Ku-band, a high FOM, low phase noise, and low power consumption 15.57 GHz CMOS VCO is designed with capacitive feedback technology to realize low phase noise and high performance. The measured phase noise at 1MHz offset is -116.6 dBc/Hz and the excellent FOM is -192.66 dBc/Hz. The tuning range is approximately 290 MHz. The power consumption is 6 mW and the chip size is 0.377 mm2.
A low-phase-noise CMOS VCO using capacitive feedback technology achieves low phase noise for K-band applications. The tuning range is from 20.817 GHz to 20.266 GHz. The measured phase noise is -115.57 dBc/Hz at 1 MHz offset. The corresponding FOM is calculated to be -190 dBc/Hz and the chip size is 0.377 mm 2.
A high-performance low-power 27 GHz CMOS VCO is designed with body-bias technology to improve the power consumption for Ka-band applications. The VCO can be tuned from 26.35 GHz to 27.102 GHz, and the measured phase noise is -106.2 dBc/Hz at 1 MHz offset frequency. The corresponding FOM is calculated to be -183.2 dBc/Hz and the chip size is 0.39 mm 2. The output power is -25.36 dBm at center oscillator frequency of 27.075 GHz.

List of Figures VII
List of Tables XI
Chapter 1 Introduction 1
1-1 Motivation 1
1-1-1 Applications 2
1-1-2 Receiver Architectures 4
1-2 Organization of the Dissertation 8
Chapter 2 Passive Devices Used in RF CMOS Design 10
2-1 Introduction 10
2-2 Inductor 10
2-2-1 Quality Factor 10
2-2-2 Design Consideration of the Inductor parameters 13
2-3 Varactor 14
Chapter 3 Design Consideration of VCOs 21
3-1 Architecture Overview 21
3-2 Oscillator Theory 22
3-2-1 Barkhausen Criteria 22
3-2-2 Negative Resistance Oscillator Theory 24
3-2-3 Startup Condition 26
3-2-4 LC-Tank and Crossed-Coupled Oscillator 27
3-3 The VCO Performance Parameters 28
3-3-1 Center Frequency 28
3-3-2 Tuning Range 29
3-3-3 Output Power 31
3-3-4 Output Amplitude 31
3-3-5 Power Dissipation 32
3-3-6 Supply and Common-Mode Rejection 32
3-4 Phase Noise in Oscillator 33
3-4-1 Definition of Phase Noise 33
3-4-2 Phase Noise Model Overview 34
3-4-3 Improvement of Phase Noise 35
Chapter 4 Circuit Design of VCOs 39
4-1 A Low-Phase-Noise and Wide-Tuning-Range CMOS VCO 39
4-1-1 Circuit Design Considerations 39
4-1-2 Simulation Results 43
4-1-3 Measurement Results 43
4-1-4 Summary 49
4-2 An 11GHz Low-Phase-Noise VCO 51
4-2-1 Circuit Design 51
4-2-2 Simulation Results 52
4-2-3 Measurement Results 56
4-2-4 Summary 57
4-3 A High Figure-of-Merit and Low
Phase Noise 15-GHz CMOS VCO 61
4-3-1 Circuit Design 61
4-3-2 Simulation Results 66
4-3-3 Measurement Results 66
4-3-4 Summary 69
4-4 A Low-Phase Noise CMOS VCO for K-Band Application 73
4-4-1 Circuit Design 73
4-4-2 Simulation Results 77
4-4-3 Measurement Results 79
4-2-4 Summary 79
4-5 A High-Performance Low-Power 27 GHz
CMOS VCO for Ka-Band Applications 83
4-5-1 Circuit Design 83
4-5-2 Simulation Results 86
4-5-3 Measurement Results 86
4-5-4 Summary 90
Chapter 5 Conclusions 92
References 94
Publication List 99

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