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研究生:黃錚
研究生(外文):Jen Huang
論文名稱:藉由路徑分析選擇電流閘控機制
論文名稱(外文):Path-Guided Power Gating Strategy Selection
指導教授:黃元欣黃元欣引用關係
指導教授(外文):Yuan--‐Shin Hwang
口試委員:黃元欣
口試日期:2012-07-25
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:43
中文關鍵詞:電源閘控
外文關鍵詞:power gating
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  • 下載下載:2
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在現行的微處理器的設計中,由於各種手持裝置、平板電腦的流行,使得能源消耗逐漸成為一個至關重要的議題。製程上的進步,也直接的影響晶片中靜態電能的消耗比率,由此衍生出各式各樣針對減少靜態電能消耗的機制。其中,本篇論文著重於探討電源閘控這項技術。電源閘控又分為兩個種類,分別是使用硬體層面控制跟軟體層面控制兩種不同的策略來減低靜態電源的消耗。本文中,利用修改過的Binary Translator透過軟體的角度觀察出合適的機制,分析出硬體策略還是軟體策略的電源閘控能夠減少更多的靜態電能消耗。

為了在軟體的層面模擬硬體電源閘控的行為,需要一個透過Path-Guided Hardware-Based Power Gating Data Flow Analysis ,來增加分析以及預測的精準度。
Power reduction is an important design consideration of microprocessor. With shrinking technologies, the percentage of leakage power on chip also increases and becomes an innegligible problem. Therefore, reducing leakage power dissipation has become an important issue. According to our observation, hardware-based power gating (HWPG) can get a better power saving than software-based power gating (SWPG), but SWPG can perform bet ter than HWPG for some special applications. Hence, we propose a path-guided hardware-based power gating selection strategy to select power gating strategy. In our approach, HWPG is the default method and then SWPG will be applied for the case that the power saving .
第一章 序論 1
1.1 研究背景 4
1.2 研究動機 7
1.3 研究目的 7
1.4 論文架構 8
第二章 文獻回顧 9
2.1 Power Gating Category 10
2.1.1 Hardware-Based Power Gating 10
2.1.2 Compiler-Based Power Gating 12
第三章 研究方法 14
3.1 概念 14
3.2 Power Gating Strategy Selection 17
3.2.1 HWPG Worst Case Candidate Picking 18
3.2.2 HWPG Worst Case Identify 20
3.3 Power Gating Strategy Selection Algorithm 22
3.4 Example 26
3.5 硬體實作 30
第四章 實驗結果 32
4.1 實驗平台 32
4.2 Energy Saving 33
第五章 結論與未來展望 38
5.1 結論 38
5.2 未來展望 38
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[7] Yi-Ping You, Chung-Wen Huang, and Jenq Kuen Lee. A sink-n-hoist framework for leakage power reduction. In EMSOFT ’05: Proceedings of the 5th ACM international conference on Embedded software, pages 124–133, New York, NY, USA, 2005. ACM.


[8] W. Zhang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and V. De“Compiler suppport for reducing leakage energy consumption,” inProc. DATE, 2003, pp. 1146–1147
[9] S. Roy, S. Katkoori, and N. Ranganathan, “A compiler based leakage reduction technique by power-gating functional units in embedded microprocessors,” in Proc. 20th Int. Conf. VLSI Des., 2007, pp. 215–220.
[10] Hailin Jiang, Malgorzata Marek-Sadowska, and Sani R. Nassif. Bene- fits and costs of power-gating technique. In ICCD ’05: Proceedings of the 2005 International Conference on Computer Design, pages 559–566, Washington, DC, USA, 2005. IEEE Computer Society.
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